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| author | Sanjin Sijaric <ssijaric@codeaurora.org> | 2016-11-07 22:39:02 +0000 |
|---|---|---|
| committer | Sanjin Sijaric <ssijaric@codeaurora.org> | 2016-11-07 22:39:02 +0000 |
| commit | 6f020d91a1cd22352cead0fdcd6b17052663c52f (patch) | |
| tree | abc707f9280f0d4653421159671fe78eaf6bdcd5 /clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp | |
| parent | 19a2308afd2ae05170e21c7213b15f5b9ebdead3 (diff) | |
| download | llvm-6f020d91a1cd22352cead0fdcd6b17052663c52f.zip llvm-6f020d91a1cd22352cead0fdcd6b17052663c52f.tar.gz llvm-6f020d91a1cd22352cead0fdcd6b17052663c52f.tar.bz2 | |
[AArch64] Transfer memory operands when lowering vector load/store intrinsics
Summary:
Some vector loads and stores generated from AArch64 intrinsics alias each other
unnecessarily, preventing better scheduling. We just need to transfer memory
operands during lowering.
Reviewers: mcrosier, t.p.northover, jmolloy
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: https://reviews.llvm.org/D26313
llvm-svn: 286168
Diffstat (limited to 'clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp')
0 files changed, 0 insertions, 0 deletions