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| author | Djordje Todorovic <djordje.todorovic@htecgroup.com> | 2024-12-19 10:01:46 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-19 10:01:46 +0100 |
| commit | 9fa109a5088bff9e8eabf6d67d0650fbd3db27cb (patch) | |
| tree | dd57b4abfd655063a15b638de1499d1ee6a9747e /clang/lib/CodeGen/ModuleBuilder.cpp | |
| parent | 023fb258b0a8f81b4eb80a8a1c8e1c48a71873de (diff) | |
| download | llvm-9fa109a5088bff9e8eabf6d67d0650fbd3db27cb.zip llvm-9fa109a5088bff9e8eabf6d67d0650fbd3db27cb.tar.gz llvm-9fa109a5088bff9e8eabf6d67d0650fbd3db27cb.tar.bz2 | |
Revert "[RISCV] Add scheduling model for mips p8700 CPU" (#120537)
Reverts llvm/llvm-project#119885
llvm-project/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td:20:5:
error: Processor does not define resources for WriteFCvtF32ToF16
def MIPSP8700Model : SchedMachineModel {
Diffstat (limited to 'clang/lib/CodeGen/ModuleBuilder.cpp')
0 files changed, 0 insertions, 0 deletions