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| author | SpencerAbson <Spencer.Abson@arm.com> | 2024-10-24 09:05:58 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-24 09:05:58 +0100 |
| commit | 17bfd21391d080afbf2697a0a1a631a1be76a2e4 (patch) | |
| tree | 9fe8400c0d109d4aef7c7badcf4bd76817526188 /clang/lib/CodeGen/CoverageMappingGen.cpp | |
| parent | 509af087cccca3bf8a90bc9871335224226dc6fe (diff) | |
| download | llvm-17bfd21391d080afbf2697a0a1a631a1be76a2e4.zip llvm-17bfd21391d080afbf2697a0a1a631a1be76a2e4.tar.gz llvm-17bfd21391d080afbf2697a0a1a631a1be76a2e4.tar.bz2 | |
[AArch64] Add assembly/disassembly for multi-vector AES instructions (#113307)
This patch adds assembly/disassembly for the following multi-vector SVE
instructions
- AESE (two/four registers)
- AESD (two/four registers)
- AESDIMC (two/four registers)
- AESEMC (two/four registers)
- Introduce assembler extension tests for the new Armv9.6 sve-aes2 and
ssve-aes features
- In accordance with:
https://developer.arm.com/documentation/ddi0602/latest/
Diffstat (limited to 'clang/lib/CodeGen/CoverageMappingGen.cpp')
0 files changed, 0 insertions, 0 deletions