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| author | CarolineConcatto <caroline.concatto@arm.com> | 2023-12-13 15:45:59 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-13 15:45:59 +0000 |
| commit | f2464ca317bfeeedddb7cbdea3c2c8ec487890bb (patch) | |
| tree | 5b0c0cb30b827d89b7aad1f4e52acbca8abbd293 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 6892c175c565e59cf485ada6b1febd41b4666414 (diff) | |
| download | llvm-f2464ca317bfeeedddb7cbdea3c2c8ec487890bb.zip llvm-f2464ca317bfeeedddb7cbdea3c2c8ec487890bb.tar.gz llvm-f2464ca317bfeeedddb7cbdea3c2c8ec487890bb.tar.bz2 | |
[SVE2.1][Clang][LLVM]Int/FP reduce builtin in Clang and LLVM intrinsic (#69926)
This patch implements the builtins in Clang
and the LLVM-IR intrinsic for the following:
// Variants are also available for:
// _s8, _s16, _u16, _s32, _u32, _s64, _u64,
// _f16, _f32, _f64uint8x16_t svaddqv[_u8](svbool_t pg, svuint8_t zn);
// Variants are also available for:
// _s8, _u16, _s16, _u32, _s32, _u64, _s64
uint8x16_t svandqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t
sveorqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t svorqv[_u8](svbool_t
pg, svuint8_t zn);
// Variants are also available for:
// _s8, _u16, _s16, _u32, _s32, _u64, _s64;
uint8x16_t svmaxqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t
svminqv[_u8](svbool_t pg, svuint8_t zn);
// Variants are also available for _f32, _f64
float16x8_t svmaxnmqv[_f16](svbool_t pg, svfloat16_t zn); float16x8_t
svminnmqv[_f16](svbool_t pg, svfloat16_t zn);
According to the PR#257[1]
The reduction instruction uses scalable vectors as input and fixed
vectors as output, therefore we changed SVEEmitter to emit fixed vector
types in case the neon header(arm_neon.h) is not present.
[1]https://github.com/ARM-software/acle/pull/257
Co-author: Dinar Temirbulatov <dinar.temirbulatov@arm.com>
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions