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| author | Craig Topper <craig.topper@sifive.com> | 2022-06-20 20:56:20 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-06-20 20:56:52 -0700 |
| commit | e01353f816999c92f41168d803af3029792663bc (patch) | |
| tree | d462b56cabee39565ef62032c342119f861255f8 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 59cde2133d8f2488171404c3e1a8fc302f0249c3 (diff) | |
| download | llvm-e01353f816999c92f41168d803af3029792663bc.zip llvm-e01353f816999c92f41168d803af3029792663bc.tar.gz llvm-e01353f816999c92f41168d803af3029792663bc.tar.bz2 | |
[RISCV] Add RISCVISD opcode for PseudoAddTPRel.
Use it along with RISCVISD::HI and ADD_LO to avoid emitting
MachineSDNodes during lowering.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions