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| author | Phoebe Wang <pengfei.wang@intel.com> | 2021-11-18 10:39:54 +0800 |
|---|---|---|
| committer | Phoebe Wang <pengfei.wang@intel.com> | 2021-11-18 11:20:32 +0800 |
| commit | de34a940ae72dfa6425a025538484f9505ca1d42 (patch) | |
| tree | fd079eea3d3d9150d729c79e9d3c18a7841a75a0 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 59c84774d21ab5a38c59d62239d37010f2a1e9cf (diff) | |
| download | llvm-de34a940ae72dfa6425a025538484f9505ca1d42.zip llvm-de34a940ae72dfa6425a025538484f9505ca1d42.tar.gz llvm-de34a940ae72dfa6425a025538484f9505ca1d42.tar.bz2 | |
[X86] Add -mskip-rax-setup support to align with GCC
AMD64 ABI mandates caller to specify the number of used SSE registers
when passing variable arguments.
GCC also provides option -mskip-rax-setup to skip the setup of rax when
SSE is disabled. This helps to reduce the code size, see pr23258.
Reviewed By: nickdesaulniers
Differential Revision: https://reviews.llvm.org/D112413
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
| -rw-r--r-- | clang/lib/CodeGen/CodeGenModule.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 1f094ed..59f3e02 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -840,6 +840,8 @@ void CodeGenModule::Release() { getCodeGenOpts().StackProtectorGuardOffset); if (getCodeGenOpts().StackAlignment) getModule().setOverrideStackAlignment(getCodeGenOpts().StackAlignment); + if (getCodeGenOpts().SkipRaxSetup) + getModule().addModuleFlag(llvm::Module::Override, "SkipRaxSetup", 1); getTargetCodeGenInfo().emitTargetMetadata(*this, MangledDeclNames); |