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| author | Luke Lau <luke@igalia.com> | 2024-07-15 23:54:00 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-15 23:54:00 +0800 |
| commit | d5f4f084d29ce95fa27e5b7e80a630ae194df4bb (patch) | |
| tree | abad99435af6a295708b6ca8273a7750cdb7a464 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 0309709a6786653da7164334c83b09c9f37b943a (diff) | |
| download | llvm-d5f4f084d29ce95fa27e5b7e80a630ae194df4bb.zip llvm-d5f4f084d29ce95fa27e5b7e80a630ae194df4bb.tar.gz llvm-d5f4f084d29ce95fa27e5b7e80a630ae194df4bb.tar.bz2 | |
[RISCV] Always expand zero strided vp.strided.load (#98901)
This patch makes zero strided VP loads always be expanded to a scalar
load and splat even if +optimized-zero-stride-load is present.
Expanding it allows more .vx splat patterns to be matched, which is
needed to prevent regressions in #98111.
If the feature is present, RISCVISelDAGToDAG will combine it back to a
zero strided load.
The RV32 test diff also shows how need to emit a zero strided load
either way after expanding an SEW=64 strided load. We could maybe fix
this in a later patch by not doing the expand if SEW>XLEN.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions