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| author | Ruiling, Song <ruiling.song@amd.com> | 2023-11-29 12:46:45 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-29 12:46:45 +0800 |
| commit | c1511a65d5c09f7cff15feba91ce9bda23d74b6e (patch) | |
| tree | 4558758981005f1ceb15ecbe83bd467a515ad94f /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | c6d6a57c697452e9320acea86f6631a92ab8017c (diff) | |
| download | llvm-c1511a65d5c09f7cff15feba91ce9bda23d74b6e.zip llvm-c1511a65d5c09f7cff15feba91ce9bda23d74b6e.tar.gz llvm-c1511a65d5c09f7cff15feba91ce9bda23d74b6e.tar.bz2 | |
[AMDGPU] Folding imm offset in more cases for scratch access (#70634)
For scratch load/store, our hardware only accept non-negative value in
SGPR/VGPR. Besides the case that we can prove from known bits, we can
also prove that the value in `base` will be non-negative: 1.) When the
ADD for the address calculation has NonUnsignedWrap flag. 2.) When the
immediate offset is already negative.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions