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| author | Craig Topper <craig.topper@sifive.com> | 2024-03-27 12:19:28 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-27 12:19:28 -0700 |
| commit | baf66ec061aa4da85d6bdfd1f9cd1030b9607fbb (patch) | |
| tree | a2a4aad09a1145ee2ad51a606c04af8c2a21e305 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | aeb8628c218f8224e08dddcdd3199a445d8607a8 (diff) | |
| download | llvm-baf66ec061aa4da85d6bdfd1f9cd1030b9607fbb.zip llvm-baf66ec061aa4da85d6bdfd1f9cd1030b9607fbb.tar.gz llvm-baf66ec061aa4da85d6bdfd1f9cd1030b9607fbb.tar.bz2 | |
[Target][RISCV] Add HwMode support to subregister index size/offset. (#86368)
This is needed to provide proper size and offset for the GPRPair subreg
indices on RISC-V. The size of a GPR already uses HwMode. Previously we
said the subreg indices have unknown size and offset, but this stops
DwarfExpression::addMachineReg from being able to find the registers
that make up the pair.
I believe this fixes https://github.com/llvm/llvm-project/issues/85864
but need to verify.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions