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| author | Craig Topper <craig.topper@sifive.com> | 2024-09-23 16:01:41 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2024-09-23 16:02:58 -0700 |
| commit | 9d3a57633ebb8251d2575696dfe53c67d3a47d33 (patch) | |
| tree | 36267aca2884a6736b148d33fb206d49720152a0 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 3734fa8c724ce2af2f69886ca97c05c6c3717c34 (diff) | |
| download | llvm-9d3a57633ebb8251d2575696dfe53c67d3a47d33.zip llvm-9d3a57633ebb8251d2575696dfe53c67d3a47d33.tar.gz llvm-9d3a57633ebb8251d2575696dfe53c67d3a47d33.tar.bz2 | |
[RISCV] Add explicit XLenVT cast to vector load/store patterns.
This seems to be needed to get the patterns to import into GISel
properly.
Unfortunately, it also adds ~400 bytes to the SelectionDAG table.
I'm hoping if we remove i32 as a legal type for GPR registers, this
will go down.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions