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| author | Alex Bradbury <asb@igalia.com> | 2023-11-29 04:48:43 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-29 04:48:43 +0000 |
| commit | 9c5003cc0c706f3cf0b13e709f41e3a64249477a (patch) | |
| tree | 7f5620597d2493122978f23231e10b7093a7fecb /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 1886b1a580240fc6aa3173f5a9344d3ead0421b6 (diff) | |
| download | llvm-9c5003cc0c706f3cf0b13e709f41e3a64249477a.zip llvm-9c5003cc0c706f3cf0b13e709f41e3a64249477a.tar.gz llvm-9c5003cc0c706f3cf0b13e709f41e3a64249477a.tar.bz2 | |
[RISCV] Implement RISCVInstrInfo::getMemOperandsWithOffsetWidth (#73681)
This hook is called by the default implementation of
getMemOperandWithOffset and by the load/store clustering code in the
MachineScheduler though this isn't enabled by default and is not yet
enabled for RISC-V. Only return true for queries on scalar loads/stores
for now (this is a conservative starting point, and vector load/store
can be handled in a follow-on patch).
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions