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| author | Craig Topper <craig.topper@sifive.com> | 2023-11-13 11:36:06 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-11-13 12:21:36 -0800 |
| commit | 915e092400f92a617a4ca7cb9f03a642bb30c7cc (patch) | |
| tree | 574fd732c8a33487570dc5ac919ad18d32f3fc6e /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 05300222bab4d48e13cc8bb5cce8c160faad47a0 (diff) | |
| download | llvm-915e092400f92a617a4ca7cb9f03a642bb30c7cc.zip llvm-915e092400f92a617a4ca7cb9f03a642bb30c7cc.tar.gz llvm-915e092400f92a617a4ca7cb9f03a642bb30c7cc.tar.bz2 | |
[RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32
In our default SelectionDAG where i32 isn't legal, the zext will become
and i64 AND and often get optimized out on its own. With i32 legal, we
need to turn it in into sext.w and rely on RISCVOptWInstrs to remove it.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions