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author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:27:26 +0300 |
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committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:28:09 +0300 |
commit | 887acf6842cb48e7c51728ed8d81fc5ab0425403 (patch) | |
tree | fd458e6b01e27f5e0791c74316e93f83ae88075c /clang/lib/CodeGen/CodeGenModule.cpp | |
parent | dd8c8d4b7cee7cb58b40e0456d656d68a31ef3b4 (diff) | |
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[X86][Costmodel] Load/store i16 Stride=6 VF=32 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/YTeT9M7fW - for intels `Block RThroughput: <=212.0`; for ryzens, `Block RThroughput: <=64.0`
So could pick cost of `212`
For store we have:
https://godbolt.org/z/vc954KEGP - for intels `Block RThroughput: <=90.0`; for ryzens, `Block RThroughput: <=24.0`
So we could pick cost of `90`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111940
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
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