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| author | Billy Zhu <billyzhu@modular.com> | 2024-08-28 09:10:17 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-28 09:10:17 -0700 |
| commit | 82113a432c5bffe026682ea117a3e2cd67a2fed0 (patch) | |
| tree | 3e430db3d76db8150ba897847b645b131f09ed21 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | ecd9e0bc901766fc22403cdf70ab2054a174b3ac (diff) | |
| download | llvm-82113a432c5bffe026682ea117a3e2cd67a2fed0.zip llvm-82113a432c5bffe026682ea117a3e2cd67a2fed0.tar.gz llvm-82113a432c5bffe026682ea117a3e2cd67a2fed0.tar.bz2 | |
[LLVM][NVPTX] Remove nonexistent ftz ops (#106100)
According to the PTX
[spec](https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-max),
max & min instructions do not support the `ftz` modifier for `bf16` &
`bf16x2` types. This PR removes them from instr info, and the non-ftz
legal versions will be emitted instead.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions