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| author | Craig Topper <craig.topper@sifive.com> | 2024-04-15 21:54:26 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-15 21:54:26 -0700 |
| commit | 65b0cc610f80d9b9724a98cf7c5bcfd38e1cf799 (patch) | |
| tree | 322d1a61b5aa7d3c2be3eecfaea88d8a83a7b283 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | fe48bf672e1ab293368a3212203db94a4e21c533 (diff) | |
| download | llvm-65b0cc610f80d9b9724a98cf7c5bcfd38e1cf799.zip llvm-65b0cc610f80d9b9724a98cf7c5bcfd38e1cf799.tar.gz llvm-65b0cc610f80d9b9724a98cf7c5bcfd38e1cf799.tar.bz2 | |
[RISCV] Add FeatureStdExtI to all CPUs in RISCVProcessors.td. NFC (#88805)
This is currently being implied in RISCVISAInfo.cpp. Make it explicit.
I'm planning to move all extension information to RISCVFeatures.td and
have tablegen create the tables for RISCVISAInfo.cpp. This requires
making the creation of RISCVTargetParserDef.inc in tablegen independent
of RISCVISAInfo.cpp. So we need an accurate extension list for CPUs in
tablegen.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions