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| author | SivanShani-Arm <sivan.shani@arm.com> | 2024-02-28 17:02:51 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-28 17:02:51 +0000 |
| commit | 634b0243b8f7acc85af4f16b70e91d86ded4dc83 (patch) | |
| tree | 70e365868319fc832c32013abaa6b3b4cb496390 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 26402777ebf4eb3d8f3d5a45943b451c740b2d76 (diff) | |
| download | llvm-634b0243b8f7acc85af4f16b70e91d86ded4dc83.zip llvm-634b0243b8f7acc85af4f16b70e91d86ded4dc83.tar.gz llvm-634b0243b8f7acc85af4f16b70e91d86ded4dc83.tar.bz2 | |
[llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116)
T1 allows for an optional registers list, the register list must be {d0-d15}.
T2 defines a mandatory register list, the register list must be {d0-d31}.
The requirements for T1/T2 are as follows:
T1 T2
Require: v8-M.Main, v8.1-M.Main,
secure state secure state
16 D Regs valid valid
32 D Regs UNDEFINED valid
No D Regs NOP NOP
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions