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| author | Craig Topper <craig.topper@sifive.com> | 2023-11-27 10:38:25 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-27 10:38:25 -0800 |
| commit | 5f31dbd18d24f0084363891139edf4fe71081eed (patch) | |
| tree | 6469fe222f6a94094776e64c92bcf711453b5e87 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 90b3e6711e0a03520fb617994178cdbe083ff20c (diff) | |
| download | llvm-5f31dbd18d24f0084363891139edf4fe71081eed.zip llvm-5f31dbd18d24f0084363891139edf4fe71081eed.tar.gz llvm-5f31dbd18d24f0084363891139edf4fe71081eed.tar.bz2 | |
[RISCV] Add register bank and instruction selection support for FP G_SELECT. (#72726)
Try to pick the FP register bank based on surrounding use/defs. Code is
basically copied from AArch64.
Need legalizer changes to make this more useful. Right now we're stuck
with only being able to FP select types less than or equal to XLen.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions