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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:27:35 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:28:09 +0300 |
| commit | 3a6a9f74d3a59beb359a9968ac27dcf97d072b3a (patch) | |
| tree | a068ba7570579c609501ce6dca5133b34039c705 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 4b76a74b4283362f69748c4d0a5bc22b1237ced0 (diff) | |
| download | llvm-3a6a9f74d3a59beb359a9968ac27dcf97d072b3a.zip llvm-3a6a9f74d3a59beb359a9968ac27dcf97d072b3a.tar.gz llvm-3a6a9f74d3a59beb359a9968ac27dcf97d072b3a.tar.bz2 | |
[X86][Costmodel] Load/store i32 Stride=4 VF=32 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/11rcvdreP - for intels `Block RThroughput: <=68.0`; for ryzens, `Block RThroughput: <=48.0`
So could pick cost of `68`
For store we have:
https://godbolt.org/z/6aM11fWcP - for intels `Block RThroughput: <=64.0`; for ryzens, `Block RThroughput: <=32.0`
So we could pick cost of `64`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111943
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
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