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authorKerry McLaughlin <kerry.mclaughlin@arm.com>2025-01-30 14:57:21 +0000
committerGitHub <noreply@github.com>2025-01-30 14:57:21 +0000
commit2fbfaff00c68139cc33b2099484b2a0dd6e60244 (patch)
tree212c54d854ea68b4266145f805a4884e88e2713e /clang/lib/CodeGen/CodeGenModule.cpp
parent59a9a8f2eadeadc2a1281fc7ae74054ca264abbb (diff)
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[AArch64][SME] Make getRegAllocationHints more specific for multi-vector loads (#123081)
getRegAllocationHints looks for ZPR2StridedOrContiguous load instructions which are used by FORM_TRANSPOSED_REG_TUPLE pseudos and adds all strided registers from this class to the list of hints. This patch changes getRegAllocationHints to restrict this list: - If the pseudo uses ZPRMul class, the first load must begin with a register which is a multiple of 2 or 4. - Only add a hint if it is part of a sequence of registers that do not already have any live intervals. This also contains changes to suggest hints when the load instructions and the FORM_TRANSPOSED pseudo use multi-vectors of different lengths, e.g. a pseudo with a 4-vector sequence of registers formed of one column extracted from four 2-vector loads.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
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