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author | David Spickett <david.spickett@linaro.org> | 2025-01-28 12:05:24 +0000 |
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committer | GitHub <noreply@github.com> | 2025-01-28 12:05:24 +0000 |
commit | c5840cc609a3674cf7453a45946f7e4a2a73590b (patch) | |
tree | cfedf002a25d5db9c262df6c68aaaa17bce6634c /clang/lib/CodeGen/CodeGenFunction.cpp | |
parent | 83433d936195c612a51b54397f82ab0d97369d86 (diff) | |
download | llvm-c5840cc609a3674cf7453a45946f7e4a2a73590b.zip llvm-c5840cc609a3674cf7453a45946f7e4a2a73590b.tar.gz llvm-c5840cc609a3674cf7453a45946f7e4a2a73590b.tar.bz2 |
[lldb][AArch64] Add register fields for Guarded Control Stack registers (#124295)
The features and locked registers hold the same bits, the latter
is a lock for the former. Tested with core files and live processes.
I thought about setting a non-zero lock register in the core file,
however:
* We can be pretty sure it's reading correctly because its between
the 2 other GCS registers in the same core file note.
* I can't make the test case modify lock bits because userspace
can't clear them (without using ptrace) and we don't know what the libc
has locked
(probably all feature bits).
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions