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| author | Craig Topper <craig.topper@sifive.com> | 2023-10-06 22:10:51 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-10-06 22:16:36 -0700 |
| commit | ee9f96bdd115e1e726e2708d791530c4d686dad2 (patch) | |
| tree | 8db340335b0b47ff4218f1901de7f685148e4f6e /clang/lib/Analysis/ThreadSafety.cpp | |
| parent | c654193c22d29c7de35004b1935b8848c43e2aa2 (diff) | |
| download | llvm-ee9f96bdd115e1e726e2708d791530c4d686dad2.zip llvm-ee9f96bdd115e1e726e2708d791530c4d686dad2.tar.gz llvm-ee9f96bdd115e1e726e2708d791530c4d686dad2.tar.bz2 | |
[RISCV][GISel] Add FPR register bank.
We need this so isel can use getRegBankFromRegClass to disambiguate
FSW and SW patterns without depending on pattern order in the tablegen
source files.
While there, add a few missing GPR register classes and sort them
in the order they appear in the tblgen output file.
Diffstat (limited to 'clang/lib/Analysis/ThreadSafety.cpp')
0 files changed, 0 insertions, 0 deletions