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| author | Craig Topper <craig.topper@sifive.com> | 2023-06-26 12:14:34 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-06-26 12:14:34 -0700 |
| commit | c32c0e14d6944d6a0e36191d7b5bf6943f96092e (patch) | |
| tree | 9448aa56319d17e8300aad9b66d78790b1a2b1c9 /clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp | |
| parent | f8927838fa85587027943c053750c403d88dae1d (diff) | |
| download | llvm-c32c0e14d6944d6a0e36191d7b5bf6943f96092e.zip llvm-c32c0e14d6944d6a0e36191d7b5bf6943f96092e.tar.gz llvm-c32c0e14d6944d6a0e36191d7b5bf6943f96092e.tar.bz2 | |
[RISCV] Add i32 as a legal type for GPR register class.
I'm investigating if it is feasible to have i32 as a legal type for RV64.
The first thing we need to do is make i32 a valid type for the GPR
register class.
We already added f32/f64 as valid types which required adding explicit
types to tablegen patterns. Adding additional types to GPR is free now.
Reviewed By: sunshaoce
Differential Revision: https://reviews.llvm.org/D151177
Diffstat (limited to 'clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp')
0 files changed, 0 insertions, 0 deletions