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| author | David Green <david.green@arm.com> | 2023-04-19 14:26:27 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2023-04-19 14:26:27 +0100 |
| commit | 139f678c7849d90eff715da99d80bbb8b75a79a5 (patch) | |
| tree | c2c993051c510522469a1d7f17838fab814f89ee /clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp | |
| parent | e6096871fdd49461687ff57c4882c76477d1d5cd (diff) | |
| download | llvm-139f678c7849d90eff715da99d80bbb8b75a79a5.zip llvm-139f678c7849d90eff715da99d80bbb8b75a79a5.tar.gz llvm-139f678c7849d90eff715da99d80bbb8b75a79a5.tar.bz2 | |
[AArch64] Remove dead tryMLAV64LaneV128 and tryMULLV64LaneV128 code.
As far as I can tell this code is never used, as the pattern recognised by
checkHighLaneIndex (an duplane with insert_subvec and extract_subvec) will not
be generated any more. There are no tests that change from removing it
(including the clang neon tests), and it didn't appear to come up in any
benchmarks I ran. There are already existing tablegen patterns for MLA with
index and s/umull with index.
Removing it also prevents it from causing problems for SVE, as in #62151.
Differential Revision: https://reviews.llvm.org/D148646
Diffstat (limited to 'clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp')
0 files changed, 0 insertions, 0 deletions