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| author | Feng Zou <feng.zou@intel.com> | 2025-04-16 10:47:05 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-16 10:47:05 +0800 |
| commit | bed03ae36600f83f214c41af333f47fe8ead9ede (patch) | |
| tree | 72edd066e55a3d89367bd8827b534da074c9f7ad /clang/lib/AST/ByteCode/Program.cpp | |
| parent | 5e9650ec2deb2f2bb6d5ad28e83bb6cd3c4189e4 (diff) | |
| download | llvm-bed03ae36600f83f214c41af333f47fe8ead9ede.zip llvm-bed03ae36600f83f214c41af333f47fe8ead9ede.tar.gz llvm-bed03ae36600f83f214c41af333f47fe8ead9ede.tar.bz2 | |
[X86] Fix the issue of creating index reg negations (#135632)
The 8 and 16 bit LEA instruction support was added by PR #122102, and we
have to update creating index register negations accordingly. The issue
is exposed with APX NDD instructions.
Diffstat (limited to 'clang/lib/AST/ByteCode/Program.cpp')
0 files changed, 0 insertions, 0 deletions