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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-04-16 06:48:56 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-16 06:48:56 +0530 |
| commit | 4c97c5131f9ca32ce644a0be6e3586077ee03aa6 (patch) | |
| tree | b3a4bce3d65d554db391e8c424494811c051dec3 /clang/lib/AST/ByteCode/Program.cpp | |
| parent | 6c6ab2a270b799f1397926c9064fa30fe2be1d96 (diff) | |
| download | llvm-4c97c5131f9ca32ce644a0be6e3586077ee03aa6.zip llvm-4c97c5131f9ca32ce644a0be6e3586077ee03aa6.tar.gz llvm-4c97c5131f9ca32ce644a0be6e3586077ee03aa6.tar.bz2 | |
[RISCV] Add ISel patterns for Xqcilia instructions (#135724)
This patch adds instruction selection patterns for generating the long
immediate arithmetic instructions.
We prefer generating instructions that have a 26 bit immediate to a 32
bit immediate given that both are of the same size but the former might
be easier to register allocate for. Base RISC-V arithmetic instructions
will be preferred, when applicable.
Diffstat (limited to 'clang/lib/AST/ByteCode/Program.cpp')
0 files changed, 0 insertions, 0 deletions