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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-04-16 11:19:13 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-16 11:19:13 +0530 |
| commit | 40460a5cf76c973a783fb2f5229e1076398df96e (patch) | |
| tree | 4ffc3932f9bf030f4a6cff1ab0716686e621367c /clang/lib/AST/ByteCode/Program.cpp | |
| parent | 3de88fe40fd0dc5f52ba0bc7ebbaf16e938d6670 (diff) | |
| download | llvm-40460a5cf76c973a783fb2f5229e1076398df96e.zip llvm-40460a5cf76c973a783fb2f5229e1076398df96e.tar.gz llvm-40460a5cf76c973a783fb2f5229e1076398df96e.tar.bz2 | |
[RISCV] Add basic ISel patterns for Xqcilo instructions (#135901)
This patch adds basic instruction selection patterns for generating the
48 bit load/store instructions that are a part of the Qualcomm uC Xqcilo
vendor extension.
Diffstat (limited to 'clang/lib/AST/ByteCode/Program.cpp')
0 files changed, 0 insertions, 0 deletions