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| author | Jim Lin <jim@andestech.com> | 2025-06-05 12:22:43 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-05 12:22:43 +0800 |
| commit | eca616f376eccfeaccb01fcfc6c833e571b7f1e1 (patch) | |
| tree | ef6b0fc44bf9f3651a88cef12ec78a2dff3ea70b /clang/lib/AST/ByteCode/Interp.cpp | |
| parent | 9d4115902351b52142db48d7e2992e9e3f620d7b (diff) | |
| download | llvm-eca616f376eccfeaccb01fcfc6c833e571b7f1e1.zip llvm-eca616f376eccfeaccb01fcfc6c833e571b7f1e1.tar.gz llvm-eca616f376eccfeaccb01fcfc6c833e571b7f1e1.tar.bz2 | |
[RISCV] Fix schedule info for Zqvdotq (#142717)
The instructions in Zqvdotq is dot-product operation. So the schedule
info should be VIMulAdd rather than VIALU.
Diffstat (limited to 'clang/lib/AST/ByteCode/Interp.cpp')
0 files changed, 0 insertions, 0 deletions