GlobalISel: mark simple ops legal even on types < 32-bit.

The 32-bit variants of these operations don't depend on the bits not being
operated on, so they also naturally model operations narrower than the actual
register width.

llvm-svn: 279760

7 files changed, 9 insertions, 28 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index 8ba6933..4e533dd 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -37,11 +37,10 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
   const LLT v2s64 = LLT::vector(2, 64);
 
   for (auto BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
-    for (auto Ty : {s32, s64, v2s32, v4s32, v2s64})
+    // These operations naturally get the right answer when used on
+    // GPR32, even if the actual type is narrower.
+    for (auto Ty : {s1, s8, s16, s32, s64, v2s32, v4s32, v2s64})
       setAction({BinOp, Ty}, Legal);
-
-    for (auto Ty : {s8, s16})
-      setAction({BinOp, Ty}, WidenScalar);
   }
 
   for (auto BinOp : {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_UDIV})
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index 924f758..18d38a3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -51,10 +51,7 @@ body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_add_small
-    ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXT { s32, s8 } %0
-    ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXT { s32, s8 } %1
-    ; CHECK: [[RES:%.*]](32) = G_ADD s32 [[LHS]], [[RHS]]
-    ; CHECK: %2(8) = G_TRUNC { s8, s32 } [[RES]]
+    ; CHECK: [[RES:%.*]](8) = G_ADD s8 %0, %1
 
     %0(8) = G_TRUNC { s8, s64 } %x0
     %1(8) = G_TRUNC { s8, s64 } %x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index aabbd8a..5a2c59b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -19,10 +19,7 @@ body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_and_small
-    ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXT { s32, s8 } %0
-    ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXT { s32, s8 } %1
-    ; CHECK: [[RES:%.*]](32) = G_AND s32 [[LHS]], [[RHS]]
-    ; CHECK: %2(8) = G_TRUNC { s8, s32 } [[RES]]
+    ; CHECK: [[RES:%.*]](8) = G_AND s8 %0, %1
 
     %0(8) = G_TRUNC { s8, s32 } %x0
     %1(8) = G_TRUNC { s8, s32 } %x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index 084543e..30991ac 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -19,10 +19,7 @@ body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_mul_small
-    ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXT { s32, s8 } %0
-    ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXT { s32, s8 } %1
-    ; CHECK: [[RES:%.*]](32) = G_MUL s32 [[LHS]], [[RHS]]
-    ; CHECK: %2(8) = G_TRUNC { s8, s32 } [[RES]]
+    ; CHECK: [[RES:%.*]](8) = G_MUL s8 %0, %1
 
     %0(8) = G_TRUNC { s8, s64 } %x0
     %1(8) = G_TRUNC { s8, s64 } %x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index 51b451b..3564b3b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -19,10 +19,7 @@ body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_or_small
-    ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXT { s32, s8 } %0
-    ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXT { s32, s8 } %1
-    ; CHECK: [[RES:%.*]](32) = G_OR s32 [[LHS]], [[RHS]]
-    ; CHECK: %2(8) = G_TRUNC { s8, s32 } [[RES]]
+    ; CHECK: %2(8) = G_OR s8 %0, %1
 
     %0(8) = G_TRUNC { s8, s64 } %x0
     %1(8) = G_TRUNC { s8, s64 } %x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index b918a2e..ec35e02 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -19,10 +19,7 @@ body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_sub_small
-    ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXT { s32, s8 } %0
-    ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXT { s32, s8 } %1
-    ; CHECK: [[RES:%.*]](32) = G_SUB s32 [[LHS]], [[RHS]]
-    ; CHECK: %2(8) = G_TRUNC { s8, s32 } [[RES]]
+    ; CHECK: [[RES:%.*]](8) = G_SUB s8 %0, %1
 
     %0(8) = G_TRUNC { s8, s64 } %x0
     %1(8) = G_TRUNC { s8, s64 } %x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 492cfdb..b1e6d5a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -19,10 +19,7 @@ body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_xor_small
-    ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXT { s32, s8 } %0
-    ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXT { s32, s8 } %1
-    ; CHECK: [[RES:%.*]](32) = G_XOR s32 [[LHS]], [[RHS]]
-    ; CHECK: %2(8) = G_TRUNC { s8, s32 } [[RES]]
+    ; CHECK: %2(8) = G_XOR s8 %0, %1
 
     %0(8) = G_TRUNC { s8, s64 } %x0
     %1(8) = G_TRUNC { s8, s64 } %x1