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| author | Stella Laurenzo <stellaraccident@gmail.com> | 2022-02-05 21:50:27 -0800 |
|---|---|---|
| committer | River Riddle <riddleriver@gmail.com> | 2022-02-06 14:51:17 -0800 |
| commit | fe23a6fb75e6ec7f2b51fb90d45ac684cc641665 (patch) | |
| tree | 0e80c028096a68ce69e42037f039efd2cc2217ac | |
| parent | ace01605e04d094c243b0cad873e8919b80a0ced (diff) | |
| download | llvm-fe23a6fb75e6ec7f2b51fb90d45ac684cc641665.zip llvm-fe23a6fb75e6ec7f2b51fb90d45ac684cc641665.tar.gz llvm-fe23a6fb75e6ec7f2b51fb90d45ac684cc641665.tar.bz2 | |
[mlir] Fixup python bindings after splitting cf ops from std.
| -rw-r--r-- | mlir/python/CMakeLists.txt | 8 | ||||
| -rw-r--r-- | mlir/python/mlir/dialects/ControlFlowOps.td | 15 | ||||
| -rw-r--r-- | mlir/python/mlir/dialects/cf.py | 5 | ||||
| -rw-r--r-- | mlir/test/python/ir/blocks.py | 5 |
4 files changed, 31 insertions, 2 deletions
diff --git a/mlir/python/CMakeLists.txt b/mlir/python/CMakeLists.txt index 59ddd83..bf379e9 100644 --- a/mlir/python/CMakeLists.txt +++ b/mlir/python/CMakeLists.txt @@ -75,6 +75,14 @@ declare_mlir_dialect_python_bindings( declare_mlir_dialect_python_bindings( ADD_TO_PARENT MLIRPythonSources.Dialects ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" + TD_FILE dialects/ControlFlowOps.td + SOURCES + dialects/cf.py + DIALECT_NAME cf) + +declare_mlir_dialect_python_bindings( + ADD_TO_PARENT MLIRPythonSources.Dialects + ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" TD_FILE dialects/GPUOps.td SOURCES_GLOB dialects/gpu/*.py DIALECT_NAME gpu) diff --git a/mlir/python/mlir/dialects/ControlFlowOps.td b/mlir/python/mlir/dialects/ControlFlowOps.td new file mode 100644 index 0000000..1bb4d41 --- /dev/null +++ b/mlir/python/mlir/dialects/ControlFlowOps.td @@ -0,0 +1,15 @@ +//===-- ControlFlowOps.td - Python ControlFlowOps bindings -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// + +#ifndef PYTHON_BINDINGS_CONTROL_FLOW_OPS +#define PYTHON_BINDINGS_CONTROL_FLOW_OPS + +include "mlir/Bindings/Python/Attributes.td" +include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.td" + +#endif diff --git a/mlir/python/mlir/dialects/cf.py b/mlir/python/mlir/dialects/cf.py new file mode 100644 index 0000000..c2e357a --- /dev/null +++ b/mlir/python/mlir/dialects/cf.py @@ -0,0 +1,5 @@ +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +from ._cf_ops_gen import * diff --git a/mlir/test/python/ir/blocks.py b/mlir/test/python/ir/blocks.py index 811dcd7..5aa1bf8 100644 --- a/mlir/test/python/ir/blocks.py +++ b/mlir/test/python/ir/blocks.py @@ -5,6 +5,7 @@ import io import itertools from mlir.ir import * from mlir.dialects import builtin +from mlir.dialects import cf # Note: std dialect needed for terminators. from mlir.dialects import std @@ -43,11 +44,11 @@ def testBlockCreation(): with InsertionPoint(entry_block) as entry_ip: assert entry_ip.block == entry_block - std.BranchOp([i16_arg], dest=middle_block) + cf.BranchOp([i16_arg], dest=middle_block) with InsertionPoint(middle_block) as middle_ip: assert middle_ip.block == middle_block - std.BranchOp([i32_arg], dest=successor_block) + cf.BranchOp([i32_arg], dest=successor_block) print(module.operation) # Ensure region back references are coherent. assert entry_block.region == middle_block.region == successor_block.region |