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| author | Jianjian Guan <jacquesguan@me.com> | 2024-04-11 10:23:26 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-11 10:23:26 +0800 |
| commit | fd50151180498f0de4fe26ff21d3e3b8accc4de0 (patch) | |
| tree | 4eb171de75758d4df67e60d79f9eec0348e69ea3 | |
| parent | f4509cf284ced95f31dc7eb63144b4bc47899c43 (diff) | |
| download | llvm-fd50151180498f0de4fe26ff21d3e3b8accc4de0.zip llvm-fd50151180498f0de4fe26ff21d3e3b8accc4de0.tar.gz llvm-fd50151180498f0de4fe26ff21d3e3b8accc4de0.tar.bz2 | |
[RISCV] Only support SPLAT_VECTOR for Zvfhmin when also enable the scalar extension of half fp (#88275)
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll | 35 |
2 files changed, 28 insertions, 10 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 944d8b6..1a3ef6f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1063,7 +1063,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, VT, Custom); - setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); + if (Subtarget.hasStdExtZfhminOrZhinxmin()) + setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); // load/store setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom); diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll index 707ef8a..1aebd32 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll @@ -1,19 +1,36 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,OPTIMIZED ; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,OPTIMIZED ; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfh,+v,+no-optimized-zero-stride-load -target-abi ilp32d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,NOT-OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,NOT-OPTIMIZED ; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfh,+v,+no-optimized-zero-stride-load -target-abi lp64d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,NOT-OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,NOT-OPTIMIZED +; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfhmin,+v -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,OPTIMIZED +; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfhmin,+v -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,OPTIMIZED +; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfhmin,+v,+no-optimized-zero-stride-load -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,NOT-OPTIMIZED +; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfhmin,+v,+no-optimized-zero-stride-load -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,NOT-OPTIMIZED define <vscale x 8 x half> @vsplat_nxv8f16(half %f) { -; CHECK-LABEL: vsplat_nxv8f16: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: ret +; ZVFH-LABEL: vsplat_nxv8f16: +; ZVFH: # %bb.0: +; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVFH-NEXT: vfmv.v.f v8, fa0 +; ZVFH-NEXT: ret +; +; ZVFHMIN-LABEL: vsplat_nxv8f16: +; ZVFHMIN: # %bb.0: +; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 +; ZVFHMIN-NEXT: ret %head = insertelement <vscale x 8 x half> poison, half %f, i32 0 %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer ret <vscale x 8 x half> %splat |