[PowerPC] Implement vector uncompress instructions (#150702)

Implement the set of vector uncompress instructions:
* vucmprhh
* vucmprlh
* vucmprhn
* vucmprln
* vucmprhb
* vucmprlb

4 files changed, 91 insertions, 0 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index e8a4e52..7277e36 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -106,6 +106,20 @@ class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,
   let Inst{21 -31} = xo;
 }
 
+class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
+                    list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> VRT;
+  bits<5> VRA;
+  bits<5> VRB;
+
+  let Pattern = pattern;
+
+  let Inst{6 -10} = VRT;
+  let Inst{11 -15} = VRA;
+  let Inst{16 -20} = VRB;
+  let Inst{21 -31} = xo;
+}
+
 let Predicates = [IsISAFuture] in {
   defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
                                  (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
@@ -159,4 +173,21 @@ let Predicates = [HasVSX, IsISAFuture] in {
   def VUPKINT4TOFP32
       : VXForm_VRTB5_UIM3<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u3imm:$UIM),
                           "vupkint4tofp32 $VRT, $VRB, $UIM", []>;
+
+  def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+                               "vucmprhn $VRT, $VRA, $VRB", []>;
+  def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+                               "vucmprln $VRT, $VRA, $VRB", []>;
+  def VUCMPRHB
+      : VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+                      "vucmprhb $VRT, $VRA, $VRB", []>;
+  def VUCMPRLB
+      : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+                      "vucmprlb $VRT, $VRA, $VRB", []>;
+  def VUCMPRHH
+      : VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+                      "vucmprhh $VRT, $VRA, $VRB", []>;
+  def VUCMPRLH
+      : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+                      "vucmprlh $VRT, $VRA, $VRB", []>;
 }
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index 6adaa5c..da3601b 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -213,3 +213,21 @@
 
 #CHECK: vupkint8tofp32 3, 5, 2
 0x10,0x6e,0x29,0x83
+
+#CHECK: vucmprhn 0, 2, 3
+0x10,0x02,0x18,0x03
+
+#CHECK: vucmprln 3, 5, 6
+0x10,0x65,0x30,0x43
+
+#CHECK: vucmprhb 1, 3, 6
+0x10,0x23,0x30,0x83
+
+#CHECK: vucmprlb 2, 4, 5
+0x10,0x44,0x28,0xC3
+
+#CHECK: vucmprlh 2, 4, 5
+0x10,0x44,0x29,0x43
+
+#CHECK: vucmprhh 1, 3, 6
+0x10,0x23,0x31,0x03
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 84f9bc8..66d0504 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -207,3 +207,21 @@
 
 #CHECK: vupkint8tofp32 3, 5, 2
 0x83,0x29,0x6e,0x10
+
+#CHECK: vucmprhn 0, 2, 3
+0x03,0x18,0x02,0x10
+
+#CHECK: vucmprln 3, 5, 6
+0x43,0x30,0x65,0x10
+
+#CHECK: vucmprhb 1, 3, 6
+0x83,0x30,0x23,0x10
+
+#CHECK: vucmprlb 2, 4, 5
+0xC3,0x28,0x44,0x10
+
+#CHECK: vucmprlh 2, 4, 5
+0x43,0x29,0x44,0x10
+
+#CHECK: vucmprhh 1, 3, 6
+0x03,0x31,0x23,0x10
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 8316bbd..6ae7bd7 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -306,3 +306,27 @@
            vupkint8tofp32 3, 5, 2
 #CHECK-BE: vupkint8tofp32 3, 5, 2         # encoding: [0x10,0x6e,0x29,0x83]
 #CHECK-LE: vupkint8tofp32 3, 5, 2         # encoding: [0x83,0x29,0x6e,0x10]
+
+           vucmprhn 0, 2, 3
+#CHECK-BE: vucmprhn 0, 2, 3                # encoding: [0x10,0x02,0x18,0x03]
+#CHECK-LE: vucmprhn 0, 2, 3                # encoding: [0x03,0x18,0x02,0x10]
+
+           vucmprln 3, 5, 6
+#CHECK-BE: vucmprln 3, 5, 6                # encoding: [0x10,0x65,0x30,0x43]
+#CHECK-LE: vucmprln 3, 5, 6                # encoding: [0x43,0x30,0x65,0x10]
+
+           vucmprhb 1, 3, 6
+#CHECK-BE: vucmprhb 1, 3, 6                # encoding: [0x10,0x23,0x30,0x83]
+#CHECK-LE: vucmprhb 1, 3, 6                # encoding: [0x83,0x30,0x23,0x10]
+
+           vucmprlb 2, 4, 5
+#CHECK-BE: vucmprlb 2, 4, 5                # encoding: [0x10,0x44,0x28,0xc3]
+#CHECK-LE: vucmprlb 2, 4, 5                # encoding: [0xc3,0x28,0x44,0x10]
+
+           vucmprlh 2, 4, 5
+#CHECK-BE: vucmprlh 2, 4, 5               # encoding: [0x10,0x44,0x29,0x43]
+#CHECK-LE: vucmprlh 2, 4, 5               # encoding: [0x43,0x29,0x44,0x10]
+
+           vucmprhh 1, 3, 6
+#CHECK-BE: vucmprhh 1, 3, 6               # encoding: [0x10,0x23,0x31,0x03]
+#CHECK-LE: vucmprhh 1, 3, 6               # encoding: [0x03,0x31,0x23,0x10]