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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-02-05 16:23:04 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-02-05 16:23:16 +0000 |
| commit | f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3 (patch) | |
| tree | d7e462d77afcfd40aa321690b1f083c447adc201 | |
| parent | 47dcf5d5dc54e62c59fedbef1e8ec3a02c77cb83 (diff) | |
| download | llvm-f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3.zip llvm-f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3.tar.gz llvm-f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3.tar.bz2 | |
[X86] printZeroUpperMove - add support for mask predicated instructions
Handle masked predicated movss/movsd in addConstantComments now that we can generically handle the destination + mask register
This will more significantly help improve 'fixup constant' comments from #73509
| -rw-r--r-- | llvm/lib/Target/X86/X86MCInstLower.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll | 6 |
2 files changed, 11 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 2690791..ec012fa 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -1561,12 +1561,14 @@ static void printConstant(const Constant *COp, unsigned BitWidth, static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer, int SclWidth, int VecWidth, const char *ShuffleComment) { + unsigned SrcIdx = getSrcIdx(MI, 1); + std::string Comment; raw_string_ostream CS(Comment); - const MachineOperand &DstOp = MI->getOperand(0); - CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; + printDstRegisterName(CS, MI, SrcIdx); + CS << " = "; - if (auto *C = X86::getConstantFromPool(*MI, 1)) { + if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) { CS << "["; printConstant(C, SclWidth, CS); for (int I = 1, E = VecWidth / SclWidth; I < E; ++I) { @@ -1863,7 +1865,7 @@ static void addConstantComments(const MachineInstr *MI, case X86::MOVSDrm: case X86::VMOVSDrm: - case X86::VMOVSDZrm: + MASK_AVX512_CASE(X86::VMOVSDZrm) case X86::MOVSDrm_alt: case X86::VMOVSDrm_alt: case X86::VMOVSDZrm_alt: @@ -1875,7 +1877,7 @@ static void addConstantComments(const MachineInstr *MI, case X86::MOVSSrm: case X86::VMOVSSrm: - case X86::VMOVSSZrm: + MASK_AVX512_CASE(X86::VMOVSSZrm) case X86::MOVSSrm_alt: case X86::VMOVSSrm_alt: case X86::VMOVSSZrm_alt: diff --git a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll index 7e1ce02e..017024c 100644 --- a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll +++ b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll @@ -6,7 +6,8 @@ define void @kmovkr_1(i1 %cmp23.not) { ; AVX512-LABEL: kmovkr_1: ; AVX512: # %bb.0: # %entry ; AVX512-NEXT: kmovw %edi, %k1 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x92,0xcf] -; AVX512-NEXT: vmovsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1} {z} # encoding: [0x62,0xf1,0xff,0x89,0x10,0x05,A,A,A,A] +; AVX512-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = [1.0E+0,0.0E+0] +; AVX512-NEXT: # encoding: [0x62,0xf1,0xff,0x89,0x10,0x05,A,A,A,A] ; AVX512-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte ; AVX512-NEXT: vmovsd %xmm0, 0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x11,0x04,0x25,0x00,0x00,0x00,0x00] ; AVX512-NEXT: retq # encoding: [0xc3] @@ -14,7 +15,8 @@ define void @kmovkr_1(i1 %cmp23.not) { ; AVX512BW-LABEL: kmovkr_1: ; AVX512BW: # %bb.0: # %entry ; AVX512BW-NEXT: kmovd %edi, %k1 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x92,0xcf] -; AVX512BW-NEXT: vmovsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k1} {z} # encoding: [0x62,0xf1,0xff,0x89,0x10,0x05,A,A,A,A] +; AVX512BW-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = [1.0E+0,0.0E+0] +; AVX512BW-NEXT: # encoding: [0x62,0xf1,0xff,0x89,0x10,0x05,A,A,A,A] ; AVX512BW-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte ; AVX512BW-NEXT: vmovsd %xmm0, 0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x11,0x04,0x25,0x00,0x00,0x00,0x00] ; AVX512BW-NEXT: retq # encoding: [0xc3] |