[Hexagon] Remove most Optionals in favor of std::optional

5 files changed, 15 insertions, 10 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h b/llvm/lib/Target/Hexagon/HexagonDepArch.h
index a564603..6a255b7 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepArch.h
+++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h
@@ -10,6 +10,7 @@
 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
 
 #include "llvm/ADT/StringSwitch.h"
+#include <optional>
 
 namespace llvm {
 namespace Hexagon {
@@ -29,8 +30,8 @@ enum class ArchEnum {
   V73
 };
 
-inline Optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
-  return StringSwitch<Optional<Hexagon::ArchEnum>>(CPU)
+inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
+  return StringSwitch<std::optional<Hexagon::ArchEnum>>(CPU)
       .Case("generic", Hexagon::ArchEnum::V5)
       .Case("hexagonv5", Hexagon::ArchEnum::V5)
       .Case("hexagonv55", Hexagon::ArchEnum::V55)
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index f74c766..72b8bb8 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -57,6 +57,7 @@
 #include <cstdint>
 #include <cstring>
 #include <iterator>
+#include <optional>
 #include <string>
 #include <utility>
 
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index fd85087..0b05b35 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -31,6 +31,7 @@
 #include <algorithm>
 #include <cassert>
 #include <map>
+#include <optional>
 
 using namespace llvm;
 
@@ -92,7 +93,7 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
 
 HexagonSubtarget &
 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
-  Optional<Hexagon::ArchEnum> ArchVer = Hexagon::getCpu(CPUString);
+  std::optional<Hexagon::ArchEnum> ArchVer = Hexagon::getCpu(CPUString);
   if (ArchVer)
     HexagonArchVersion = *ArchVer;
   else
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
index 6858885..536ef9b 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
@@ -28,6 +28,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cassert>
+#include <optional>
 #include <utility>
 #include <vector>
 
@@ -316,7 +317,7 @@ void HexagonShuffler::permitNonSlot() {
 }
 
 bool HexagonShuffler::ValidResourceUsage(HexagonPacketSummary const &Summary) {
-  Optional<HexagonPacket> ShuffledPacket = tryAuction(Summary);
+  std::optional<HexagonPacket> ShuffledPacket = tryAuction(Summary);
 
   if (!ShuffledPacket) {
     reportResourceError(Summary, "slot error");
@@ -623,7 +624,7 @@ bool HexagonShuffler::check(const bool RequireShuffle) {
   return !CheckFailure;
 }
 
-llvm::Optional<HexagonShuffler::HexagonPacket>
+std::optional<HexagonShuffler::HexagonPacket>
 HexagonShuffler::tryAuction(HexagonPacketSummary const &Summary) {
   HexagonPacket PacketResult = Packet;
   HexagonUnitAuction AuctionCore(Summary.ReservedSlotMask);
@@ -642,7 +643,7 @@ HexagonShuffler::tryAuction(HexagonPacketSummary const &Summary) {
              << llvm::format_hex(ISJ.Core.getUnits(), 4, true) << "\n";
   );
 
-  Optional<HexagonPacket> Res;
+  std::optional<HexagonPacket> Res;
   if (ValidSlots)
     Res = PacketResult;
 
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
index 70992e4..66303cb 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
@@ -24,6 +24,7 @@
 #include "llvm/Support/SMLoc.h"
 #include <cstdint>
 #include <functional>
+#include <optional>
 #include <utility>
 
 namespace llvm {
@@ -148,12 +149,12 @@ class HexagonShuffler {
     // Number of duplex insns
     unsigned duplex;
     unsigned pSlot3Cnt;
-    Optional<HexagonInstr *> PrefSlot3Inst;
+    std::optional<HexagonInstr *> PrefSlot3Inst;
     unsigned memops;
     unsigned ReservedSlotMask;
     SmallVector<HexagonInstr *, HEXAGON_PRESHUFFLE_PACKET_SIZE> branchInsts;
-    Optional<SMLoc> Slot1AOKLoc;
-    Optional<SMLoc> NoSlot1StoreLoc;
+    std::optional<SMLoc> Slot1AOKLoc;
+    std::optional<SMLoc> NoSlot1StoreLoc;
   };
   // Insn handles in a bundle.
   HexagonPacket Packet;
@@ -179,7 +180,7 @@ protected:
                            const bool DoShuffle);
   void permitNonSlot();
 
-  Optional<HexagonPacket> tryAuction(HexagonPacketSummary const &Summary);
+  std::optional<HexagonPacket> tryAuction(HexagonPacketSummary const &Summary);
 
   HexagonPacketSummary GetPacketSummary();
   bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const;