aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-09-09 16:55:49 -0400
committerMatt Arsenault <arsenm2@gmail.com>2020-01-06 17:21:51 -0500
commitee6b8722ffa101b57af9029c84691cb7e8a43799 (patch)
treebb79e7554e33bd00aa9c7b041debe49a85857bca
parent1060b9e23b8f9d2802835896947ec281ba3b4f6b (diff)
downloadllvm-ee6b8722ffa101b57af9029c84691cb7e8a43799.zip
llvm-ee6b8722ffa101b57af9029c84691cb7e8a43799.tar.gz
llvm-ee6b8722ffa101b57af9029c84691cb7e8a43799.tar.bz2
GlobalISel: Fix unsupported legalize action
This would complain about invalid legalizer rules otherwise. Mark some operations as unsupported for AMDGPU. This currently seems to produce the same legalize error as when no rules are defined, but eventually this should produce a proper user facing error.
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h1
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp5
-rw-r--r--llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir78
3 files changed, 84 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 642f882..29f0d65 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -661,6 +661,7 @@ public:
/// The instruction is unsupported.
LegalizeRuleSet &unsupported() {
+ markAllIdxsAsCovered();
return actionIf(LegalizeAction::Unsupported, always);
}
LegalizeRuleSet &unsupportedIf(LegalityPredicate Predicate) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 2e459e1..3498abe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1101,6 +1101,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder(G_SEXT_INREG).lower();
+ getActionDefinitionsBuilder({G_VASTART, G_VAARG, G_BRJT, G_JUMP_TABLE,
+ G_DYN_STACKALLOC, G_INDEXED_LOAD, G_INDEXED_SEXTLOAD,
+ G_INDEXED_ZEXTLOAD, G_INDEXED_STORE})
+ .unsupported();
+
computeTables();
verify(*ST.getInstrInfo());
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
new file mode 100644
index 0000000..40e5ccd
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
@@ -0,0 +1,78 @@
+# RUN: not llc -march=amdgcn -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck %s
+
+# CHECK: LLVM ERROR: unable to legalize instruction: %3:_(p0) = G_JUMP_TABLE %jump-table.0 (in function: jt_test)
+
+# FIXME: This could probably be smaller, but the jump table MIR parsing is very crashy.
+
+--- |
+ define i32 @jt_test(i32 %x) {
+ entry:
+ switch i32 %x, label %return [
+ i32 75, label %sw.bb
+ i32 34, label %sw.bb
+ i32 56, label %sw.bb
+ i32 35, label %sw.bb
+ i32 40, label %sw.bb
+ i32 4, label %sw.bb1
+ i32 5, label %sw.bb1
+ i32 6, label %sw.bb1
+ ]
+
+ sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
+ %add = add nsw i32 %x, 42
+ br label %return
+
+ sw.bb1: ; preds = %entry, %entry, %entry
+ %mul = mul nsw i32 %x, 3
+ br label %return
+
+ return: ; preds = %sw.bb1, %sw.bb, %entry
+ %retval.0 = phi i32 [ %mul, %sw.bb1 ], [ %add, %sw.bb ], [ 0, %entry ]
+ ret i32 %retval.0
+ }
+
+...
+---
+name: jt_test
+tracksRegLiveness: true
+jumpTable:
+ kind: block-address
+ entries:
+ - id: 0
+ blocks: [ '%bb.3', '%bb.3', '%bb.3', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.2', '%bb.2', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.2', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
+ '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2' ]
+body: |
+ bb.0.entry:
+ liveins: $sgpr0
+
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s1) = G_ICMP intpred(ugt), %0, %1
+ %3:_(p0) = G_JUMP_TABLE %jump-table.0
+ S_NOP 0, implicit %3
+ G_BRCOND %2, %bb.4
+
+ bb.1.entry:
+ successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
+
+ G_BR %bb.4
+
+ bb.2.sw.bb:
+ G_BR %bb.4
+
+ bb.3.sw.bb1:
+
+ bb.4.return:
+ S_ENDPGM 0
+
+...