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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-11-19 15:37:52 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-11-19 15:37:52 +0000 |
| commit | e8ea92d24e2ba785bf633de913258829132e9d7a (patch) | |
| tree | 86351c57955a959261c2cc71b414cbbe023f6481 | |
| parent | 88be0a21975b8f6fb5e48c86ba86543315794d6b (diff) | |
| download | llvm-e8ea92d24e2ba785bf633de913258829132e9d7a.zip llvm-e8ea92d24e2ba785bf633de913258829132e9d7a.tar.gz llvm-e8ea92d24e2ba785bf633de913258829132e9d7a.tar.bz2 | |
[X86] Remove some unnecessary cvt overrides
All of these match the default WriteCvtI2PS class defs
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedIceLake.td | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 17 |
2 files changed, 8 insertions, 26 deletions
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td index ce9e254..040d2af 100644 --- a/llvm/lib/Target/X86/X86SchedIceLake.td +++ b/llvm/lib/Target/X86/X86SchedIceLake.td @@ -973,39 +973,30 @@ def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[ICXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", - "(V?)CVTDQ2PSrr", - "VCVTPD2QQ(Z128|Z256)rr", +def: InstRW<[ICXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr", "VCVTPD2UQQ(Z128|Z256)rr", "VCVTPS2DQ(Y|Z128|Z256)rr", "(V?)CVTPS2DQrr", "VCVTPS2UDQ(Z128|Z256)rr", - "VCVTQQ2PD(Z128|Z256)rr", "VCVTTPD2QQ(Z128|Z256)rr", "VCVTTPD2UQQ(Z128|Z256)rr", "VCVTTPS2DQ(Z128|Z256)rr", "(V?)CVTTPS2DQrr", - "VCVTTPS2UDQ(Z128|Z256)rr", - "VCVTUDQ2PS(Z128|Z256)rr", - "VCVTUQQ2PD(Z128|Z256)rr")>; + "VCVTTPS2UDQ(Z128|Z256)rr")>; def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> { let Latency = 4; let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[ICXWriteResGroup50z], (instrs VCVTDQ2PSZrr, - VCVTPD2QQZrr, +def: InstRW<[ICXWriteResGroup50z], (instrs VCVTPD2QQZrr, VCVTPD2UQQZrr, VCVTPS2DQZrr, VCVTPS2UDQZrr, - VCVTQQ2PDZrr, VCVTTPD2QQZrr, VCVTTPD2UQQZrr, VCVTTPS2DQZrr, - VCVTTPS2UDQZrr, - VCVTUDQ2PSZrr, - VCVTUQQ2PDZrr)>; + VCVTTPS2UDQZrr)>; def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> { let Latency = 4; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index c4b5ebe..7d45b17 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -955,39 +955,30 @@ def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", - "(V?)CVTDQ2PSrr", - "VCVTPD2QQ(Z128|Z256)rr", +def: InstRW<[SKXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr", "VCVTPD2UQQ(Z128|Z256)rr", "VCVTPS2DQ(Y|Z128|Z256)rr", "(V?)CVTPS2DQrr", "VCVTPS2UDQ(Z128|Z256)rr", - "VCVTQQ2PD(Z128|Z256)rr", "VCVTTPD2QQ(Z128|Z256)rr", "VCVTTPD2UQQ(Z128|Z256)rr", "VCVTTPS2DQ(Z128|Z256)rr", "(V?)CVTTPS2DQrr", - "VCVTTPS2UDQ(Z128|Z256)rr", - "VCVTUDQ2PS(Z128|Z256)rr", - "VCVTUQQ2PD(Z128|Z256)rr")>; + "VCVTTPS2UDQ(Z128|Z256)rr")>; def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> { let Latency = 4; let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr, - VCVTPD2QQZrr, +def: InstRW<[SKXWriteResGroup50z], (instrs VCVTPD2QQZrr, VCVTPD2UQQZrr, VCVTPS2DQZrr, VCVTPS2UDQZrr, - VCVTQQ2PDZrr, VCVTTPD2QQZrr, VCVTTPD2UQQZrr, VCVTTPS2DQZrr, - VCVTTPS2UDQZrr, - VCVTUDQ2PSZrr, - VCVTUQQ2PDZrr)>; + VCVTTPS2UDQZrr)>; def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { let Latency = 4; |