[RISCV] Add coverage for vector stack slot coloring and dead copy elim

Stack slot coloring already works, but we didn't have coverage.
Dead stack slot copy elimination (after stack slot coloring) does not, and will
be included in an upcoming change.

2 files changed, 806 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.ll b/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.ll
new file mode 100644
index 0000000..579c012
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.ll
@@ -0,0 +1,478 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+
+declare void @foo()
+
+define void @test_m1(ptr %p, ptr %p2) {
+; RV32-LABEL: test_m1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -48
+; RV32-NEXT:    .cfi_def_cfa_offset 48
+; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    .cfi_offset s1, -12
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    sub sp, sp, a2
+; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 1 * vlenb
+; RV32-NEXT:    mv s0, a0
+; RV32-NEXT:    vl1r.v v8, (a0)
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    mv s1, a1
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs1r.v v8, (s0)
+; RV32-NEXT:    vl1r.v v8, (s1)
+; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs1r.v v8, (s1)
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    add sp, sp, a0
+; RV32-NEXT:    .cfi_def_cfa sp, 48
+; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_restore ra
+; RV32-NEXT:    .cfi_restore s0
+; RV32-NEXT:    .cfi_restore s1
+; RV32-NEXT:    addi sp, sp, 48
+; RV32-NEXT:    .cfi_def_cfa_offset 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_m1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi sp, sp, -64
+; RV64-NEXT:    .cfi_def_cfa_offset 64
+; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s1, 40(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    .cfi_offset s1, -24
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    sub sp, sp, a2
+; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 1 * vlenb
+; RV64-NEXT:    mv s0, a0
+; RV64-NEXT:    vl1r.v v8, (a0)
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    mv s1, a1
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs1r.v v8, (s0)
+; RV64-NEXT:    vl1r.v v8, (s1)
+; RV64-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs1r.v v8, (s1)
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    add sp, sp, a0
+; RV64-NEXT:    .cfi_def_cfa sp, 64
+; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_restore ra
+; RV64-NEXT:    .cfi_restore s0
+; RV64-NEXT:    .cfi_restore s1
+; RV64-NEXT:    addi sp, sp, 64
+; RV64-NEXT:    .cfi_def_cfa_offset 0
+; RV64-NEXT:    ret
+  %v1 = load <vscale x 8 x i8>, ptr %p
+  call void @foo();
+  store <vscale x 8 x i8> %v1, ptr %p
+  %v2 = load <vscale x 8 x i8>, ptr %p2
+  call void @foo();
+  store <vscale x 8 x i8> %v2, ptr %p2
+  ret void
+}
+
+define void @test_m2(ptr %p, ptr %p2) {
+; RV32-LABEL: test_m2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -48
+; RV32-NEXT:    .cfi_def_cfa_offset 48
+; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    .cfi_offset s1, -12
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a2, a2, 1
+; RV32-NEXT:    sub sp, sp, a2
+; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb
+; RV32-NEXT:    mv s0, a0
+; RV32-NEXT:    vl2r.v v8, (a0)
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    mv s1, a1
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs2r.v v8, (s0)
+; RV32-NEXT:    vl2r.v v8, (s1)
+; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs2r.v v8, (s1)
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    slli a0, a0, 1
+; RV32-NEXT:    add sp, sp, a0
+; RV32-NEXT:    .cfi_def_cfa sp, 48
+; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_restore ra
+; RV32-NEXT:    .cfi_restore s0
+; RV32-NEXT:    .cfi_restore s1
+; RV32-NEXT:    addi sp, sp, 48
+; RV32-NEXT:    .cfi_def_cfa_offset 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_m2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi sp, sp, -64
+; RV64-NEXT:    .cfi_def_cfa_offset 64
+; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s1, 40(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    .cfi_offset s1, -24
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a2, a2, 1
+; RV64-NEXT:    sub sp, sp, a2
+; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
+; RV64-NEXT:    mv s0, a0
+; RV64-NEXT:    vl2r.v v8, (a0)
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    mv s1, a1
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs2r.v v8, (s0)
+; RV64-NEXT:    vl2r.v v8, (s1)
+; RV64-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs2r.v v8, (s1)
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    slli a0, a0, 1
+; RV64-NEXT:    add sp, sp, a0
+; RV64-NEXT:    .cfi_def_cfa sp, 64
+; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_restore ra
+; RV64-NEXT:    .cfi_restore s0
+; RV64-NEXT:    .cfi_restore s1
+; RV64-NEXT:    addi sp, sp, 64
+; RV64-NEXT:    .cfi_def_cfa_offset 0
+; RV64-NEXT:    ret
+  %v1 = load <vscale x 16 x i8>, ptr %p
+  call void @foo();
+  store <vscale x 16 x i8> %v1, ptr %p
+  %v2 = load <vscale x 16 x i8>, ptr %p2
+  call void @foo();
+  store <vscale x 16 x i8> %v2, ptr %p2
+  ret void
+}
+
+define void @test_m8(ptr %p, ptr %p2) {
+; RV32-LABEL: test_m8:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -48
+; RV32-NEXT:    .cfi_def_cfa_offset 48
+; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    .cfi_offset s1, -12
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a2, a2, 3
+; RV32-NEXT:    sub sp, sp, a2
+; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 8 * vlenb
+; RV32-NEXT:    mv s0, a0
+; RV32-NEXT:    vl8r.v v8, (a0)
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    mv s1, a1
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs8r.v v8, (s0)
+; RV32-NEXT:    vl8r.v v8, (s1)
+; RV32-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs8r.v v8, (s1)
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    slli a0, a0, 3
+; RV32-NEXT:    add sp, sp, a0
+; RV32-NEXT:    .cfi_def_cfa sp, 48
+; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_restore ra
+; RV32-NEXT:    .cfi_restore s0
+; RV32-NEXT:    .cfi_restore s1
+; RV32-NEXT:    addi sp, sp, 48
+; RV32-NEXT:    .cfi_def_cfa_offset 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_m8:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi sp, sp, -64
+; RV64-NEXT:    .cfi_def_cfa_offset 64
+; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s1, 40(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    .cfi_offset s1, -24
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a2, a2, 3
+; RV64-NEXT:    sub sp, sp, a2
+; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 8 * vlenb
+; RV64-NEXT:    mv s0, a0
+; RV64-NEXT:    vl8r.v v8, (a0)
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    mv s1, a1
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs8r.v v8, (s0)
+; RV64-NEXT:    vl8r.v v8, (s1)
+; RV64-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs8r.v v8, (s1)
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    slli a0, a0, 3
+; RV64-NEXT:    add sp, sp, a0
+; RV64-NEXT:    .cfi_def_cfa sp, 64
+; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_restore ra
+; RV64-NEXT:    .cfi_restore s0
+; RV64-NEXT:    .cfi_restore s1
+; RV64-NEXT:    addi sp, sp, 64
+; RV64-NEXT:    .cfi_def_cfa_offset 0
+; RV64-NEXT:    ret
+  %v1 = load <vscale x 64 x i8>, ptr %p
+  call void @foo();
+  store <vscale x 64 x i8> %v1, ptr %p
+  %v2 = load <vscale x 64 x i8>, ptr %p2
+  call void @foo();
+  store <vscale x 64 x i8> %v2, ptr %p2
+  ret void
+}
+
+define void @test_m1_then_m1(ptr %p, ptr %p2) {
+; RV32-LABEL: test_m1_then_m1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -48
+; RV32-NEXT:    .cfi_def_cfa_offset 48
+; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    .cfi_offset s1, -12
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a2, a2, 1
+; RV32-NEXT:    sub sp, sp, a2
+; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb
+; RV32-NEXT:    mv s0, a0
+; RV32-NEXT:    vl2r.v v8, (a0)
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    mv s1, a1
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs2r.v v8, (s0)
+; RV32-NEXT:    vl1r.v v8, (s1)
+; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs1r.v v8, (s1)
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    slli a0, a0, 1
+; RV32-NEXT:    add sp, sp, a0
+; RV32-NEXT:    .cfi_def_cfa sp, 48
+; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_restore ra
+; RV32-NEXT:    .cfi_restore s0
+; RV32-NEXT:    .cfi_restore s1
+; RV32-NEXT:    addi sp, sp, 48
+; RV32-NEXT:    .cfi_def_cfa_offset 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_m1_then_m1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi sp, sp, -64
+; RV64-NEXT:    .cfi_def_cfa_offset 64
+; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s1, 40(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    .cfi_offset s1, -24
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a2, a2, 1
+; RV64-NEXT:    sub sp, sp, a2
+; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
+; RV64-NEXT:    mv s0, a0
+; RV64-NEXT:    vl2r.v v8, (a0)
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    mv s1, a1
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs2r.v v8, (s0)
+; RV64-NEXT:    vl1r.v v8, (s1)
+; RV64-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs1r.v v8, (s1)
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    slli a0, a0, 1
+; RV64-NEXT:    add sp, sp, a0
+; RV64-NEXT:    .cfi_def_cfa sp, 64
+; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_restore ra
+; RV64-NEXT:    .cfi_restore s0
+; RV64-NEXT:    .cfi_restore s1
+; RV64-NEXT:    addi sp, sp, 64
+; RV64-NEXT:    .cfi_def_cfa_offset 0
+; RV64-NEXT:    ret
+  %v1 = load <vscale x 16 x i8>, ptr %p
+  call void @foo();
+  store <vscale x 16 x i8> %v1, ptr %p
+  %v2 = load <vscale x 8 x i8>, ptr %p2
+  call void @foo();
+  store <vscale x 8 x i8> %v2, ptr %p2
+  ret void
+}
+
+define void @test_m1_then_m2(ptr %p, ptr %p2) {
+; RV32-LABEL: test_m1_then_m2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -48
+; RV32-NEXT:    .cfi_def_cfa_offset 48
+; RV32-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    .cfi_offset s1, -12
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a2, a2, 1
+; RV32-NEXT:    sub sp, sp, a2
+; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb
+; RV32-NEXT:    mv s0, a0
+; RV32-NEXT:    vl1r.v v8, (a0)
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    mv s1, a1
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs1r.v v8, (s0)
+; RV32-NEXT:    vl2r.v v8, (s1)
+; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV32-NEXT:    call foo
+; RV32-NEXT:    addi a0, sp, 32
+; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-NEXT:    vs2r.v v8, (s1)
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    slli a0, a0, 1
+; RV32-NEXT:    add sp, sp, a0
+; RV32-NEXT:    .cfi_def_cfa sp, 48
+; RV32-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_restore ra
+; RV32-NEXT:    .cfi_restore s0
+; RV32-NEXT:    .cfi_restore s1
+; RV32-NEXT:    addi sp, sp, 48
+; RV32-NEXT:    .cfi_def_cfa_offset 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_m1_then_m2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi sp, sp, -64
+; RV64-NEXT:    .cfi_def_cfa_offset 64
+; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s1, 40(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    .cfi_offset s1, -24
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a2, a2, 1
+; RV64-NEXT:    sub sp, sp, a2
+; RV64-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
+; RV64-NEXT:    mv s0, a0
+; RV64-NEXT:    vl1r.v v8, (a0)
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    mv s1, a1
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs1r.v v8, (s0)
+; RV64-NEXT:    vl2r.v v8, (s1)
+; RV64-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
+; RV64-NEXT:    call foo
+; RV64-NEXT:    addi a0, sp, 32
+; RV64-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-NEXT:    vs2r.v v8, (s1)
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    slli a0, a0, 1
+; RV64-NEXT:    add sp, sp, a0
+; RV64-NEXT:    .cfi_def_cfa sp, 64
+; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_restore ra
+; RV64-NEXT:    .cfi_restore s0
+; RV64-NEXT:    .cfi_restore s1
+; RV64-NEXT:    addi sp, sp, 64
+; RV64-NEXT:    .cfi_def_cfa_offset 0
+; RV64-NEXT:    ret
+  %v1 = load <vscale x 8 x i8>, ptr %p
+  call void @foo();
+  store <vscale x 8 x i8> %v1, ptr %p
+  %v2 = load <vscale x 16 x i8>, ptr %p2
+  call void @foo();
+  store <vscale x 16 x i8> %v2, ptr %p2
+  ret void
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir b/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir
new file mode 100644
index 0000000..6cf6307
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir
@@ -0,0 +1,328 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc %s -mtriple=riscv64 -mattr=+v -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - | FileCheck %s
+
+---
+name:            nop_copy_elim_m1
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    4
+  localFrameSize:  4
+stack:
+  - { id: 0, size: 1, alignment: 4, local-offset: -4 }
+machineFunctionInfo:
+  varArgsFrameIndex: 0
+  varArgsSaveSize: 0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: nop_copy_elim_m1
+    ; CHECK: $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v30 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.1 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.1 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v0, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v1, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v2, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v3, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v4, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v5, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v6, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v7, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v8, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v9, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v10, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v11, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v12, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v13, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v14, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v15, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v16, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v17, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v18, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v19, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v20, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v21, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v22, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v23, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v24, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v25, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v26, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v27, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v28, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v29, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v30, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: PseudoRET
+    $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v30 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+
+    %0:vr = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    %1:vr = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    VS1R_V %1:vr, %stack.0 :: (volatile store unknown-size)
+
+    %2:vr = COPY %0:vr
+
+    %3:vr = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    VS1R_V %3:vr, %stack.0 :: (volatile store unknown-size)
+    VS1R_V %2:vr, %stack.0 :: (volatile store unknown-size)
+
+    VS1R_V $v0, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v1, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v2, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v3, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v4, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v5, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v6, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v7, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v8, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v9, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v10, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v11, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v12, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v13, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v14, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v15, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v16, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v17, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v18, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v19, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v20, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v21, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v22, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v23, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v24, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v25, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v26, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v27, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v28, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v29, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v30, %stack.0 :: (volatile store unknown-size)
+    PseudoRET
+
+...
+---
+name:            nop_copy_elim_m2
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    4
+  localFrameSize:  4
+stack:
+  - { id: 0, size: 1, alignment: 4, local-offset: -4 }
+machineFunctionInfo:
+  varArgsFrameIndex: 0
+  varArgsSaveSize: 0
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: nop_copy_elim_m2
+    ; CHECK: $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.0 :: (volatile load unknown-size, align 1)
+    ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v0, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v1, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v2, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v3, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v4, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v5, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v6, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v7, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v8, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v9, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v10, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v11, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v12, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v13, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v14, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v15, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v16, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v17, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v18, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v19, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v20, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v21, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v22, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v23, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v24, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v25, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v26, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v27, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v28, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: VS1R_V $v29, %stack.0 :: (volatile store unknown-size, align 1)
+    ; CHECK-NEXT: PseudoRET
+    $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+    $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size)
+
+    %0:vrm2 = VL2RE8_V %stack.0 :: (volatile load unknown-size)
+    %1:vrm2 = VL2RE8_V %stack.0 :: (volatile load unknown-size)
+    VS2R_V %1:vrm2, %stack.0 :: (volatile store unknown-size)
+
+    %2:vrm2 = COPY %0:vrm2
+
+    %3:vrm2 = VL2RE8_V %stack.0 :: (volatile load unknown-size)
+    VS2R_V %3:vrm2, %stack.0 :: (volatile store unknown-size)
+    VS2R_V %2:vrm2, %stack.0 :: (volatile store unknown-size)
+
+    VS1R_V $v0, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v1, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v2, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v3, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v4, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v5, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v6, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v7, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v8, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v9, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v10, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v11, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v12, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v13, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v14, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v15, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v16, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v17, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v18, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v19, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v20, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v21, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v22, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v23, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v24, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v25, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v26, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v27, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v28, %stack.0 :: (volatile store unknown-size)
+    VS1R_V $v29, %stack.0 :: (volatile store unknown-size)
+    PseudoRET
+
+...
+