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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-04-08 16:37:44 -0400 |
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committer | Matt Arsenault <arsenm2@gmail.com> | 2020-04-08 17:03:53 -0400 |
commit | e49e33b6102880f15856e7820fb6d9f0e2ef83d6 (patch) | |
tree | 85df4fb5b4308c9cc5244e7af02f7c733589bd8c | |
parent | 6fb6a4d7f972d8faacd6b2646fe15f2eea1e4915 (diff) | |
download | llvm-e49e33b6102880f15856e7820fb6d9f0e2ef83d6.zip llvm-e49e33b6102880f15856e7820fb6d9f0e2ef83d6.tar.gz llvm-e49e33b6102880f15856e7820fb6d9f0e2ef83d6.tar.bz2 |
CodeGen: Use Register in MachineInstrBuilder
-rw-r--r-- | llvm/include/llvm/CodeGen/MachineInstrBundle.h | 4 | ||||
-rw-r--r-- | llvm/lib/CodeGen/MachineInstrBundle.cpp | 29 |
2 files changed, 16 insertions, 17 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBundle.h b/llvm/include/llvm/CodeGen/MachineInstrBundle.h index 517f03e..8a73f9a 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBundle.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBundle.h @@ -238,7 +238,7 @@ struct VirtRegInfo { /// each operand referring to Reg. /// @returns A filled-in RegInfo struct. VirtRegInfo AnalyzeVirtRegInBundle( - MachineInstr &MI, unsigned Reg, + MachineInstr &MI, Register Reg, SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops = nullptr); /// Information about how a physical register Reg is used by a set of @@ -281,7 +281,7 @@ struct PhysRegInfo { /// /// @param Reg The physical register to analyze. /// @returns A filled-in PhysRegInfo struct. -PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, unsigned Reg, +PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI); } // End llvm namespace diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp index 94865b0..50456e4 100644 --- a/llvm/lib/CodeGen/MachineInstrBundle.cpp +++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp @@ -136,14 +136,14 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB, BuildMI(MF, getDebugLoc(FirstMI, LastMI), TII->get(TargetOpcode::BUNDLE)); Bundle.prepend(MIB); - SmallVector<unsigned, 32> LocalDefs; - SmallSet<unsigned, 32> LocalDefSet; - SmallSet<unsigned, 8> DeadDefSet; - SmallSet<unsigned, 16> KilledDefSet; - SmallVector<unsigned, 8> ExternUses; - SmallSet<unsigned, 8> ExternUseSet; - SmallSet<unsigned, 8> KilledUseSet; - SmallSet<unsigned, 8> UndefUseSet; + SmallVector<Register, 32> LocalDefs; + SmallSet<Register, 32> LocalDefSet; + SmallSet<Register, 8> DeadDefSet; + SmallSet<Register, 16> KilledDefSet; + SmallVector<Register, 8> ExternUses; + SmallSet<Register, 8> ExternUseSet; + SmallSet<Register, 8> KilledUseSet; + SmallSet<Register, 8> UndefUseSet; SmallVector<MachineOperand*, 4> Defs; for (auto MII = FirstMI; MII != LastMI; ++MII) { for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) { @@ -207,9 +207,9 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB, Defs.clear(); } - SmallSet<unsigned, 32> Added; + SmallSet<Register, 32> Added; for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) { - unsigned Reg = LocalDefs[i]; + Register Reg = LocalDefs[i]; if (Added.insert(Reg).second) { // If it's not live beyond end of the bundle, mark it dead. bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg); @@ -219,7 +219,7 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB, } for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) { - unsigned Reg = ExternUses[i]; + Register Reg = ExternUses[i]; bool isKill = KilledUseSet.count(Reg); bool isUndef = UndefUseSet.count(Reg); MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | @@ -279,7 +279,7 @@ bool llvm::finalizeBundles(MachineFunction &MF) { } VirtRegInfo llvm::AnalyzeVirtRegInBundle( - MachineInstr &MI, unsigned Reg, + MachineInstr &MI, Register Reg, SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops) { VirtRegInfo RI = {false, false, false}; for (MIBundleOperands O(MI); O.isValid(); ++O) { @@ -308,13 +308,12 @@ VirtRegInfo llvm::AnalyzeVirtRegInBundle( return RI; } -PhysRegInfo llvm::AnalyzePhysRegInBundle(const MachineInstr &MI, unsigned Reg, +PhysRegInfo llvm::AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI) { bool AllDefsDead = true; PhysRegInfo PRI = {false, false, false, false, false, false, false, false}; - assert(Register::isPhysicalRegister(Reg) && - "analyzePhysReg not given a physical register!"); + assert(Reg.isPhysical() && "analyzePhysReg not given a physical register!"); for (ConstMIBundleOperands O(MI); O.isValid(); ++O) { const MachineOperand &MO = *O; |