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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-08 14:12:19 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-09 10:29:31 -0500 |
| commit | db7c92077963195df0807e976cc916b5c6e29a05 (patch) | |
| tree | 3c073039babe074e9111321a4d04f52f531b3198 | |
| parent | 9704ba652a0062c53ec66b068766df5c0cd5c620 (diff) | |
| download | llvm-db7c92077963195df0807e976cc916b5c6e29a05.zip llvm-db7c92077963195df0807e976cc916b5c6e29a05.tar.gz llvm-db7c92077963195df0807e976cc916b5c6e29a05.tar.bz2 | |
AMDGPU: Add register class to DS_SWIZZLE_B32 pattern
Reduces diff for a future patch.
| -rw-r--r-- | llvm/lib/Target/AMDGPU/DSInstructions.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index f008b80..f0987cf 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -619,7 +619,7 @@ def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">; def : GCNPat < (int_amdgcn_ds_swizzle i32:$src, timm:$offset16), - (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0)) + (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16imm $offset16), (i1 0)) >; class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat < |