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| author | Sirish Pande <sirpande@amd.com> | 2023-09-20 11:37:18 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-20 11:37:18 -0500 |
| commit | cc3491fd452ca916e8041641b5e03091c844b3fb (patch) | |
| tree | 32b3d75a6759d6e3b9baa83b57c0533dfd5af9ac | |
| parent | 46a1908c2625ecfb5a080c97cab63e6cd3662d2b (diff) | |
| download | llvm-cc3491fd452ca916e8041641b5e03091c844b3fb.zip llvm-cc3491fd452ca916e8041641b5e03091c844b3fb.tar.gz llvm-cc3491fd452ca916e8041641b5e03091c844b3fb.tar.bz2 | |
[SelectionDAG] [NFC] Add pre-commit test for PR66701. (#66796)
[SelectionDAG] [NFC] Add pre-commit test for PR66701.
Co-authored-by: Sirish Pande <sirish.pande@amd.com>
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/fma.ll | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/fma.ll b/llvm/test/CodeGen/AMDGPU/fma.ll index b1db04a..0f8560c 100644 --- a/llvm/test/CodeGen/AMDGPU/fma.ll +++ b/llvm/test/CodeGen/AMDGPU/fma.ll @@ -154,3 +154,27 @@ define float @fold_fmul_distributive(float %x, float %y) { %fmul = fmul contract float %fadd, %x ret float %fmul } + +; test to make sure contract is not dropped such that we can generate fma from following mul/add +define amdgpu_kernel void @vec_mul_scalar_add_fma(<2 x float> %a, <2 x float> %b, float %c1, ptr addrspace(1) %inptr) { +; GFX906-LABEL: vec_mul_scalar_add_fma: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX906-NEXT: s_waitcnt lgkmcnt(0) +; GFX906-NEXT: s_load_dword s5, s[0:1], 0x34 +; GFX906-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c +; GFX906-NEXT: v_mov_b32_e32 v0, 0 +; GFX906-NEXT: v_mov_b32_e32 v1, s6 +; GFX906-NEXT: v_mul_f32_e32 v1, s4, v1 +; GFX906-NEXT: s_waitcnt lgkmcnt(0) +; GFX906-NEXT: v_add_f32_e32 v1, s5, v1 +; GFX906-NEXT: global_store_dword v0, v1, s[2:3] offset:4 +; GFX906-NEXT: s_endpgm + %gep = getelementptr float, ptr addrspace(1) %inptr, i32 1 + %c = shufflevector <2 x float> %a, <2 x float> poison, <2 x i32> zeroinitializer + %mul = fmul contract <2 x float> %c, %b + %elv = extractelement <2 x float> %mul, i64 0 + %add = fadd contract float %elv, %c1 + store float %add, ptr addrspace(1) %gep, align 4 + ret void +} |