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| author | Akshat Oke <76596238+optimisan@users.noreply.github.com> | 2024-10-14 14:37:21 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-14 14:37:21 +0530 |
| commit | bec839d8eed9dd13fa7eaffd50b28f8f913de2e2 (patch) | |
| tree | 18c1fcb7c492212ed91d4f64a3dbf6211c750046 | |
| parent | 0cfa6e2092846f11a1534af4c928df3c61d73eb0 (diff) | |
| download | llvm-bec839d8eed9dd13fa7eaffd50b28f8f913de2e2.zip llvm-bec839d8eed9dd13fa7eaffd50b28f8f913de2e2.tar.gz llvm-bec839d8eed9dd13fa7eaffd50b28f8f913de2e2.tar.bz2 | |
[AMDGPU] Serialize WWM_REG vreg flag (#110229)
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir | 15 |
4 files changed, 44 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 23ee0c3..16e2387 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -1718,6 +1718,17 @@ bool GCNTargetMachine::parseMachineFunctionInfo( MFI->reserveWWMRegister(ParsedReg); } + for (const auto &[_, Info] : PFS.VRegInfosNamed) { + for (uint8_t Flag : Info->Flags) { + MFI->setFlag(Info->VReg, Flag); + } + } + for (const auto &[_, Info] : PFS.VRegInfos) { + for (uint8_t Flag : Info->Flags) { + MFI->setFlag(Info->VReg, Flag); + } + } + auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A, const TargetRegisterClass &RC, ArgDescriptor &Arg, unsigned UserSGPRs, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index de9cbe4..20d48aa 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -3851,3 +3851,13 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const TargetRegisterClass *RC, } return 0; } + +SmallVector<StringLiteral> +SIRegisterInfo::getVRegFlagsOfReg(Register Reg, + const MachineFunction &MF) const { + SmallVector<StringLiteral> RegFlags; + const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>(); + if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) + RegFlags.push_back("WWM_REG"); + return RegFlags; +} diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 99fa632..fe0b66f75 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -457,6 +457,14 @@ public: // No check if the subreg is supported by the current RC is made. unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC, unsigned SubReg) const; + + std::optional<uint8_t> getVRegFlagValue(StringRef Name) const override { + return Name == "WWM_REG" ? AMDGPU::VirtRegFlag::WWM_REG + : std::optional<uint8_t>{}; + } + + SmallVector<StringLiteral> + getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override; }; namespace AMDGPU { diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir index ebbb89b7..51795a4 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -578,3 +578,18 @@ body: | SI_RETURN ... +--- +name: vregs +# FULL: registers: +# FULL-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1', flags: [ WWM_REG ] } +# FULL-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1', flags: [ ] } +# FULL-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ] } +registers: + - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]} + - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 } + - { id: 2, class: sgpr_64, flags: [ ] } +body: | + bb.0: + %2:sgpr_64 = COPY %1 + %1:sgpr_64 = COPY %0 +... |