Refactor isThumb1Only() && isMClass() into a predicate called isV6M()

This must be enforced for all v6M cores, not just the cortex-m0,
irregardless of the user-specified alignment.

Patch by Charlie Turner.

llvm-svn: 219300

2 files changed, 8 insertions, 5 deletions

diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 5d052c08..a26fba1 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -310,15 +310,14 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
       (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
                       isTargetNetBSD())) ||
       (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
-    // The one exception is cortex-m0, which despite being v6, does not
-    // support unaligned accesses. Rather than make the above boolean
-    // expression even more obtuse, just override the value here.
-    if (isThumb1Only() && isMClass())
-      AllowsUnalignedMem = false;
   } else {
     AllowsUnalignedMem = !(Align == StrictAlign);
   }
 
+  // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
+  if (isV6M())
+    AllowsUnalignedMem = false;
+
   switch (IT) {
   case DefaultIT:
     RestrictIT = hasV8Ops() ? true : false;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index c6e756c..8c85ad7 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -405,6 +405,10 @@ public:
   bool isRClass() const { return ARMProcClass == RClass; }
   bool isAClass() const { return ARMProcClass == AClass; }
 
+  bool isV6M() const {
+    return isThumb1Only() && isMClass();
+  }
+
   bool isR9Reserved() const { return IsR9Reserved; }
 
   bool useMovt(const MachineFunction &MF) const;