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| author | David Green <david.green@arm.com> | 2025-05-20 09:59:41 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-20 09:59:41 +0100 |
| commit | b95ad8eca6ae1ef73b4ee3018b69446995f39353 (patch) | |
| tree | 187fe286a957cccfb97c01e644b2be9bfb8e3130 | |
| parent | 32cf55aef3f83723616e27d149ea0186d73481b0 (diff) | |
| download | llvm-b95ad8eca6ae1ef73b4ee3018b69446995f39353.zip llvm-b95ad8eca6ae1ef73b4ee3018b69446995f39353.tar.gz llvm-b95ad8eca6ae1ef73b4ee3018b69446995f39353.tar.bz2 | |
[DAGCombine] Use isLegalExtLoad for MatchLoadCombine (#140536)
This looks wrong to me, but I don't have a test case where it alters the
generated code.
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 68693ce..531f6fb 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9482,8 +9482,8 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) { // split into legal sized loads. This enables us to combine i64 load by i8 // patterns to a couple of i32 loads on 32 bit targets. if (LegalOperations && - !TLI.isOperationLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, - MemVT)) + !TLI.isLoadExtLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, VT, + MemVT)) return SDValue(); // Check if the bytes of the OR we are looking at match with either big or |