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| author | YunQiang Su <yunqiang@isrc.iscas.ac.cn> | 2025-02-18 17:14:29 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-18 17:14:29 +0800 |
| commit | b8054104d36d0b26b2a445d61ba12cf0fe6ba805 (patch) | |
| tree | 9f58bc81e39dc09dc945c39132dc8d7e4e7decfd | |
| parent | 9fec0a0942f5a11f4dcfec20aa485a8513661720 (diff) | |
| download | llvm-b8054104d36d0b26b2a445d61ba12cf0fe6ba805.zip llvm-b8054104d36d0b26b2a445d61ba12cf0fe6ba805.tar.gz llvm-b8054104d36d0b26b2a445d61ba12cf0fe6ba805.tar.bz2 | |
LLVM/Test: Mark Mips readcyclecounter.ll XFAIL: expensive_checks (#127587)
expsensive_check complains that:
bb.0.entry:
%0:gpr32 = RDHWR $hwr2, 0
%1:gpr32 = ADDiu $zero, 0
$v0 = COPY %0:gpr32
$v1 = COPY %1:gpr32
RetRA implicit $v0, implicit $v1
*** Bad machine code: Using an undefined physical register ***
- function: test_readcyclecounter
- basic block: %bb.0 entry (0xad97ee0)
- instruction: %0:gpr32 = RDHWR $hwr2, 0
- operand 1: $hwr2
LLVM ERROR: Found 1 machine code errors.
| -rw-r--r-- | llvm/test/CodeGen/Mips/readcyclecounter.ll | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/readcyclecounter.ll b/llvm/test/CodeGen/Mips/readcyclecounter.ll index 467dd92..23d3ea0 100644 --- a/llvm/test/CodeGen/Mips/readcyclecounter.ll +++ b/llvm/test/CodeGen/Mips/readcyclecounter.ll @@ -7,6 +7,8 @@ ;RUN: llc -mtriple=mipsel -mcpu=mips2 < %s | FileCheck %s --check-prefix=MIPSEL_NOT_SUPPORTED ;RUN: llc -mtriple=mips64el -mcpu=mips3 < %s | FileCheck %s --check-prefix=MIPS64EL_NOT_SUPPORTED +; XFAIL: expensive_checks + declare i64 @llvm.readcyclecounter() nounwind readnone define i64 @test_readcyclecounter() nounwind { |