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| author | Craig Topper <craig.topper@sifive.com> | 2023-06-07 12:48:43 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-06-07 12:50:26 -0700 |
| commit | b03e6e65e7430e032fca58f0982d1918a0ccba08 (patch) | |
| tree | 84ab2ed413874233f49e63e87cd87f7da61a29c5 | |
| parent | c10a7772bd7603cb6b252ef89e2009fa0c60dc94 (diff) | |
| download | llvm-b03e6e65e7430e032fca58f0982d1918a0ccba08.zip llvm-b03e6e65e7430e032fca58f0982d1918a0ccba08.tar.gz llvm-b03e6e65e7430e032fca58f0982d1918a0ccba08.tar.bz2 | |
[RISCV] Change riscv_vid_vl isel pattern to use _MASK instruction.
The post isel peephole can convert it to the unmasked form.
We don't have any way to test the masked version right now because
we always use a true mask.
This makes the isel pattern consistent with many other instructions
that select the mask form.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 71df6e4..aecfab6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -2476,9 +2476,11 @@ def riscv_fslide1down_vl : SDNode<"RISCVISD::VFSLIDE1DOWN_VL", SDTRVVFSlide1, [ foreach vti = AllIntegerVectors in { let Predicates = GetVTypePredicates<vti>.Predicates in { - def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), + def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask V0), VLOpFrag)), - (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; + (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX#"_MASK") + (vti.Vector (IMPLICIT_DEF)), (vti.Mask V0), GPR:$vl, vti.Log2SEW, + TAIL_AGNOSTIC)>; def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef), (vti.Vector vti.RegClass:$rs1), |