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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-04-07 15:13:46 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-04-07 15:24:45 +0100 |
| commit | afa1ae9e0c0bb7bacca65ebd43ecb21d3848bbe4 (patch) | |
| tree | 33d26fa9e002c910a1922807bbeb678486f1ab9c | |
| parent | 00b293e83f6bb84f970eea972f022d578923d832 (diff) | |
| download | llvm-afa1ae9e0c0bb7bacca65ebd43ecb21d3848bbe4.zip llvm-afa1ae9e0c0bb7bacca65ebd43ecb21d3848bbe4.tar.gz llvm-afa1ae9e0c0bb7bacca65ebd43ecb21d3848bbe4.tar.bz2 | |
[InstCombine] SimplifyDemandedUseBits - allow and(srem(X,Pow2),C) -> and(X,C) to work on vector types
Replace m_ConstantInt with m_APInt to match uniform (no-undef) vector remainder amounts.
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll | 5 |
2 files changed, 6 insertions, 7 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 96c59c7..278db05 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -739,13 +739,13 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, break; } case Instruction::SRem: { - ConstantInt *Rem; - if (match(I->getOperand(1), m_ConstantInt(Rem))) { + const APInt *Rem; + if (match(I->getOperand(1), m_APInt(Rem))) { // X % -1 demands all the bits because we don't want to introduce // INT_MIN % -1 (== undef) by accident. - if (Rem->isMinusOne()) + if (Rem->isAllOnes()) break; - APInt RA = Rem->getValue().abs(); + APInt RA = Rem->abs(); if (RA.isPowerOf2()) { if (DemandedMask.ult(RA)) // srem won't affect demanded bits return I->getOperand(0); diff --git a/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll b/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll index 67c489c..0038abe 100644 --- a/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll +++ b/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll @@ -17,9 +17,8 @@ entry: define <2 x i32> @a_vec(<2 x i32> %b) nounwind { ; CHECK-LABEL: @a_vec( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = srem <2 x i32> [[B:%.*]], <i32 8, i32 8> -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TMP0]], <i32 1, i32 1> -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[TMP0:%.*]] = and <2 x i32> [[B:%.*]], <i32 1, i32 1> +; CHECK-NEXT: ret <2 x i32> [[TMP0]] ; entry: srem <2 x i32> %b, <i32 8, i32 8> |