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| author | Craig Topper <craig.topper@gmail.com> | 2020-02-06 21:31:44 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2020-02-06 21:32:53 -0800 |
| commit | ae4e49868ac35dda3b02441a11f3cc3edf4d383b (patch) | |
| tree | c0ae572a20befb3adb7271303c6fa497917f0804 | |
| parent | 3f62028f2f3a904e608945147ebddc7051c0d6f9 (diff) | |
| download | llvm-ae4e49868ac35dda3b02441a11f3cc3edf4d383b.zip llvm-ae4e49868ac35dda3b02441a11f3cc3edf4d383b.tar.gz llvm-ae4e49868ac35dda3b02441a11f3cc3edf4d383b.tar.bz2 | |
[X86] Turn vXi1 any_extends into sign_extends in PreprocessISelDAG and remove some isel patterns.
Similar to what we do for other vector any_extends, but instead
of zero_extend we need to use sign_extend.
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 12 |
2 files changed, 11 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 53e9f34..d91363a 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -879,13 +879,19 @@ void X86DAGToDAGISel::PreprocessISelDAG() { case ISD::ANY_EXTEND_VECTOR_INREG: { // Replace vector any extend with the zero extend equivalents so we don't // need 2 sets of patterns. Ignore vXi1 extensions. - if (!N->getValueType(0).isVector() || - N->getOperand(0).getScalarValueSizeInBits() == 1) + if (!N->getValueType(0).isVector()) break; - unsigned NewOpc = N->getOpcode() == ISD::ANY_EXTEND - ? ISD::ZERO_EXTEND - : ISD::ZERO_EXTEND_VECTOR_INREG; + unsigned NewOpc; + if (N->getOperand(0).getScalarValueSizeInBits() == 1) { + assert(N->getOpcode() == ISD::ANY_EXTEND && + "Unexpected opcode for mask vector!"); + NewOpc = ISD::SIGN_EXTEND; + } else { + NewOpc = N->getOpcode() == ISD::ANY_EXTEND + ? ISD::ZERO_EXTEND + : ISD::ZERO_EXTEND_VECTOR_INREG; + } SDValue Res = CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0), N->getOperand(0)); diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 4c2ee5d..9f616f8 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -9804,10 +9804,6 @@ def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src), !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"), [(set Vec.RC:$dst, (Vec.VT (sext Vec.KRC:$src)))]>, EVEX, Sched<[WriteMove]>; // TODO - WriteVecTrunc? - -// Also need a pattern for anyextend. -def : Pat<(Vec.VT (anyext Vec.KRC:$src)), - (!cast<Instruction>(NAME#"rr") Vec.KRC:$src)>; } multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo, @@ -9881,19 +9877,11 @@ let Predicates = [HasDQI, NoBWI] in { (VPMOVDBZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; def : Pat<(v16i16 (sext (v16i1 VK16:$src))), (VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; - - def : Pat<(v16i8 (anyext (v16i1 VK16:$src))), - (VPMOVDBZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; - def : Pat<(v16i16 (anyext (v16i1 VK16:$src))), - (VPMOVDWZrr (v16i32 (VPMOVM2DZrr VK16:$src)))>; } let Predicates = [HasDQI, NoBWI, HasVLX] in { def : Pat<(v8i16 (sext (v8i1 VK8:$src))), (VPMOVDWZ256rr (v8i32 (VPMOVM2DZ256rr VK8:$src)))>; - - def : Pat<(v8i16 (anyext (v8i1 VK8:$src))), - (VPMOVDWZ256rr (v8i32 (VPMOVM2DZ256rr VK8:$src)))>; } //===----------------------------------------------------------------------===// |