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authorLuke <luke957@foxmail.com>2021-09-01 13:08:13 +0800
committerLuke <luke957@foxmail.com>2021-09-01 14:25:15 +0800
commita78dd726f46de63529585b2569314d35ce39105d (patch)
treea838ef8fdf733f89d25964a9d01bca74cf905d42
parent199344d832c1bed1d75b1db2c1493e5a3e5c5544 (diff)
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[SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D108973
-rw-r--r--llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 4853351..b1d0e38 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -73,6 +73,10 @@ public:
llvm_unreachable("Unsupported register kind");
}
+ unsigned getMinVectorRegisterBitWidth() const {
+ return ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0;
+ }
+
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
const Value *Ptr, bool VariableMask,
Align Alignment,