[X86][NFC] Added/Updated Trigonometric functions testcases (#127094)

- Added sin/cos testcases.
- Added i686 checks for all testcases.
- Moved fp16 and fp128 cases into separate files.
- Dropped tests for ppc_fp128 type.
- Added global-isel runs as precommit testing for #126931

12 files changed, 1309 insertions, 410 deletions

diff --git a/llvm/test/CodeGen/X86/fp128-libcalls.ll b/llvm/test/CodeGen/X86/fp128-libcalls.ll
index bb75ec1..0831675 100644
--- a/llvm/test/CodeGen/X86/fp128-libcalls.ll
+++ b/llvm/test/CodeGen/X86/fp128-libcalls.ll
@@ -921,3 +921,271 @@ entry:
   ret fp128 %call
 }
 declare fp128 @llvm.fma.f128(fp128, fp128, fp128)
+
+define fp128 @Test128Acos(fp128 %a) nounwind {
+; ANDROID-LABEL: Test128Acos:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp acosl@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Acos:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp acosf128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Acos:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll acosl
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.acos.f128(fp128 %a)
+  ret fp128 %x
+}
+
+define fp128 @Test128Asin(fp128 %a) nounwind {
+; ANDROID-LABEL: Test128Asin:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp asinl@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Asin:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp asinf128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Asin:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll asinl
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.asin.f128(fp128 %a)
+  ret fp128 %x
+}
+
+define fp128 @Test128Atan(fp128 %a) nounwind {
+; ANDROID-LABEL: Test128Atan:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp atanl@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Atan:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp atanf128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Atan:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll atanl
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.atan.f128(fp128 %a)
+  ret fp128 %x
+}
+
+define fp128 @Test128Atan2(fp128 %a, fp128 %b) nounwind {
+; ANDROID-LABEL: Test128Atan2:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp atan2l@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Atan2:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp atan2f128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Atan2:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll atan2l
+; X86-NEXT:    addl $44, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.atan2.f128(fp128 %a, fp128 %b)
+  ret fp128 %x
+}
+
+define fp128 @Test128Cosh(fp128 %a) nounwind {
+; ANDROID-LABEL: Test128Cosh:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp coshl@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Cosh:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp coshf128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Cosh:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll coshl
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.cosh.f128(fp128 %a)
+  ret fp128 %x
+}
+
+define fp128 @Test128Sinh(fp128 %a) nounwind {
+; ANDROID-LABEL: Test128Sinh:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp sinhl@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Sinh:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp sinhf128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Sinh:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll sinhl
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.sinh.f128(fp128 %a)
+  ret fp128 %x
+}
+
+define fp128 @Test128Tan(fp128 %a) nounwind {
+; ANDROID-LABEL: Test128Tan:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp tanl@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Tan:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp tanf128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Tan:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll tanl
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.tan.f128(fp128 %a)
+  ret fp128 %x
+}
+
+define fp128 @Test128Tanh(fp128 %a) nounwind {
+; ANDROID-LABEL: Test128Tanh:
+; ANDROID:       # %bb.0:
+; ANDROID-NEXT:    jmp tanhl@PLT # TAILCALL
+;
+; GNU-LABEL: Test128Tanh:
+; GNU:       # %bb.0:
+; GNU-NEXT:    jmp tanhf128@PLT # TAILCALL
+;
+; X86-LABEL: Test128Tanh:
+; X86:       # %bb.0:
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $24, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl {{[0-9]+}}(%esp)
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    calll tanhl
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    movaps (%esp), %xmm0
+; X86-NEXT:    movaps %xmm0, (%esi)
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    addl $24, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    retl $4
+  %x = call fp128 @llvm.tanh.f128(fp128 %a)
+  ret fp128 %x
+}
diff --git a/llvm/test/CodeGen/X86/fp16-libcalls.ll b/llvm/test/CodeGen/X86/fp16-libcalls.ll
index 3af8b1a..57db963 100644
--- a/llvm/test/CodeGen/X86/fp16-libcalls.ll
+++ b/llvm/test/CodeGen/X86/fp16-libcalls.ll
@@ -1188,3 +1188,472 @@ define void @test_half_trunc(half %a0, ptr %p0) nounwind {
   store half %res, ptr %p0, align 2
   ret void
 }
+
+define half @test_half_acos(half %a) nounwind {
+; F16C-LABEL: test_half_acos:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq acosf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test_half_acos:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq acosf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test_half_acos:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq acosf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test_half_acos:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll acosf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.acos.f16(half %a)
+  ret half %x
+}
+
+define half @test_half_asin(half %a) nounwind {
+; F16C-LABEL: test_half_asin:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq asinf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test_half_asin:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq asinf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test_half_asin:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq asinf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test_half_asin:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll asinf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.asin.f16(half %a)
+  ret half %x
+}
+
+define half @test_half_atan(half %a) nounwind {
+; F16C-LABEL: test_half_atan:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq atanf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test_half_atan:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq atanf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test_half_atan:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq atanf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test_half_atan:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll atanf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.atan.f16(half %a)
+  ret half %x
+}
+
+define half @test_half_atan2(half %a, half %b) nounwind {
+; F16C-LABEL: test_half_atan2:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    vcvtph2ps %xmm1, %xmm1
+; F16C-NEXT:    callq atan2f@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test_half_atan2:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    vcvtsh2ss %xmm1, %xmm1, %xmm1
+; FP16-NEXT:    callq atan2f@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test_half_atan2:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; X64-NEXT:    movaps %xmm1, %xmm0
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    movss %xmm0, (%rsp) # 4-byte Spill
+; X64-NEXT:    movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; X64-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    movss (%rsp), %xmm1 # 4-byte Reload
+; X64-NEXT:    # xmm1 = mem[0],zero,zero,zero
+; X64-NEXT:    callq atan2f@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test_half_atan2:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $60, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; X86-NEXT:    movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps {{[0-9]+}}(%esp)
+; X86-NEXT:    fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll atan2f
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $60, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.atan2.f16(half %a, half %b)
+  ret half %x
+}
+
+define half @test2_half_cos(half %Val) nounwind {
+; F16C-LABEL: test2_half_cos:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq cosf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test2_half_cos:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq cosf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test2_half_cos:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq cosf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test2_half_cos:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll cosf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %res = call half @llvm.cos.f16(half %Val)
+  ret half %res
+}
+
+define half @test_half_cosh(half %a) nounwind {
+; F16C-LABEL: test_half_cosh:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq coshf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test_half_cosh:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq coshf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test_half_cosh:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq coshf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test_half_cosh:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll coshf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.cosh.f16(half %a)
+  ret half %x
+}
+
+define half @test2_half_sin(half %Val) nounwind {
+; F16C-LABEL: test2_half_sin:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq sinf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test2_half_sin:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq sinf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test2_half_sin:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq sinf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test2_half_sin:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll sinf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %res = call half @llvm.sin.f16(half %Val)
+  ret half %res
+}
+
+define half @test_half_sinh(half %a) nounwind {
+; F16C-LABEL: test_half_sinh:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq sinhf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test_half_sinh:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq sinhf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test_half_sinh:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq sinhf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test_half_sinh:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll sinhf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.sinh.f16(half %a)
+  ret half %x
+}
+
+define half @test2_half_tan(half %a) nounwind {
+; F16C-LABEL: test2_half_tan:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq tanf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test2_half_tan:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq tanf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test2_half_tan:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq tanf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test2_half_tan:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll tanf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.tan.f16(half %a)
+  ret half %x
+}
+
+define half @test_half_tanh(half %a) nounwind {
+; F16C-LABEL: test_half_tanh:
+; F16C:       # %bb.0:
+; F16C-NEXT:    pushq %rax
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    callq tanhf@PLT
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    popq %rax
+; F16C-NEXT:    retq
+;
+; FP16-LABEL: test_half_tanh:
+; FP16:       # %bb.0:
+; FP16-NEXT:    pushq %rax
+; FP16-NEXT:    vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    callq tanhf@PLT
+; FP16-NEXT:    vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT:    popq %rax
+; FP16-NEXT:    retq
+;
+; X64-LABEL: test_half_tanh:
+; X64:       # %bb.0:
+; X64-NEXT:    pushq %rax
+; X64-NEXT:    callq __extendhfsf2@PLT
+; X64-NEXT:    callq tanhf@PLT
+; X64-NEXT:    callq __truncsfhf2@PLT
+; X64-NEXT:    popq %rax
+; X64-NEXT:    retq
+;
+; X86-LABEL: test_half_tanh:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:    pextrw $0, %xmm0, %eax
+; X86-NEXT:    movw %ax, (%esp)
+; X86-NEXT:    calll __extendhfsf2
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll tanhf
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll __truncsfhf2
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+  %x = call half @llvm.tanh.f16(half %a)
+  ret half %x
+}
diff --git a/llvm/test/CodeGen/X86/llvm.acos.ll b/llvm/test/CodeGen/X86/llvm.acos.ll
index 202fde8..9ae6749 100644
--- a/llvm/test/CodeGen/X86/llvm.acos.ll
+++ b/llvm/test/CodeGen/X86/llvm.acos.ll
@@ -1,70 +1,70 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_acosf16(half %a) nounwind {
-; CHECK-LABEL: use_acosf16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    callq acosf@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.acos.f16(half %a)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_acosf32(float %a) nounwind {
-; CHECK-LABEL: use_acosf32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp acosf@PLT # TAILCALL
+; X86-LABEL: use_acosf32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll acosf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_acosf32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp acosf@PLT # TAILCALL
   %x = call float @llvm.acos.f32(float %a)
   ret float %x
 }
 
 define double @use_acosf64(double %a) nounwind {
-; CHECK-LABEL: use_acosf64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp acos@PLT # TAILCALL
+; X86-LABEL: use_acosf64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll acos
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_acosf64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp acos@PLT # TAILCALL
   %x = call double @llvm.acos.f64(double %a)
   ret double %x
 }
 
 define x86_fp80 @use_acosf80(x86_fp80 %a) nounwind {
-; CHECK-LABEL: use_acosf80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:    fldt 32(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq acosl@PLT
-; CHECK-NEXT:    addq  $24, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_acosf80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll acosl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_acosf80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq acosl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.acos.f80(x86_fp80 %a)
   ret x86_fp80 %x
 }
 
-define fp128 @use_acosfp128(fp128 %a) nounwind {
-; CHECK-LABEL: use_acosfp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp  acosf128@PLT # TAILCALL
-  %x = call fp128 @llvm.acos.f128(fp128 %a)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_acosppc_fp128(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: use_acosppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq acosl@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.acos.ppcf128(ppc_fp128 %a)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.acos.f16(half)
 declare float @llvm.acos.f32(float)
 declare double @llvm.acos.f64(double)
 declare x86_fp80 @llvm.acos.f80(x86_fp80)
-declare fp128 @llvm.acos.f128(fp128)
-declare ppc_fp128 @llvm.acos.ppcf128(ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.asin.ll b/llvm/test/CodeGen/X86/llvm.asin.ll
index 1e047d0..f17e33a 100644
--- a/llvm/test/CodeGen/X86/llvm.asin.ll
+++ b/llvm/test/CodeGen/X86/llvm.asin.ll
@@ -1,70 +1,70 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_asinf16(half %a) nounwind {
-; CHECK-LABEL: use_asinf16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    callq asinf@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.asin.f16(half %a)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_asinf32(float %a) nounwind {
-; CHECK-LABEL: use_asinf32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp asinf@PLT # TAILCALL
+; X86-LABEL: use_asinf32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll asinf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_asinf32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp asinf@PLT # TAILCALL
   %x = call float @llvm.asin.f32(float %a)
   ret float %x
 }
 
 define double @use_asinf64(double %a) nounwind {
-; CHECK-LABEL: use_asinf64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp asin@PLT # TAILCALL
+; X86-LABEL: use_asinf64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll asin
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_asinf64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp asin@PLT # TAILCALL
   %x = call double @llvm.asin.f64(double %a)
   ret double %x
 }
 
 define x86_fp80 @use_asinf80(x86_fp80 %a) nounwind {
-; CHECK-LABEL: use_asinf80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:    fldt 32(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq asinl@PLT
-; CHECK-NEXT:    addq  $24, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_asinf80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll asinl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_asinf80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq asinl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.asin.f80(x86_fp80 %a)
   ret x86_fp80 %x
 }
 
-define fp128 @use_asinfp128(fp128 %a) nounwind {
-; CHECK-LABEL: use_asinfp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp  asinf128@PLT # TAILCALL
-  %x = call fp128 @llvm.asin.f128(fp128 %a)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_asinppc_fp128(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: use_asinppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq asinl@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.asin.ppcf128(ppc_fp128 %a)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.asin.f16(half)
 declare float @llvm.asin.f32(float)
 declare double @llvm.asin.f64(double)
 declare x86_fp80 @llvm.asin.f80(x86_fp80)
-declare fp128 @llvm.asin.f128(fp128)
-declare ppc_fp128 @llvm.asin.ppcf128(ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.atan.ll b/llvm/test/CodeGen/X86/llvm.atan.ll
index d33ef7f..013b5e7 100644
--- a/llvm/test/CodeGen/X86/llvm.atan.ll
+++ b/llvm/test/CodeGen/X86/llvm.atan.ll
@@ -1,70 +1,70 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_atanf16(half %a) nounwind {
-; CHECK-LABEL: use_atanf16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    callq atanf@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.atan.f16(half %a)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_atanf32(float %a) nounwind {
-; CHECK-LABEL: use_atanf32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp atanf@PLT # TAILCALL
+; X86-LABEL: use_atanf32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll atanf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_atanf32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp atanf@PLT # TAILCALL
   %x = call float @llvm.atan.f32(float %a)
   ret float %x
 }
 
 define double @use_atanf64(double %a) nounwind {
-; CHECK-LABEL: use_atanf64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp atan@PLT # TAILCALL
+; X86-LABEL: use_atanf64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll atan
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_atanf64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp atan@PLT # TAILCALL
   %x = call double @llvm.atan.f64(double %a)
   ret double %x
 }
 
 define x86_fp80 @use_atanf80(x86_fp80 %a) nounwind {
-; CHECK-LABEL: use_atanf80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:    fldt 32(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq atanl@PLT
-; CHECK-NEXT:    addq  $24, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_atanf80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll atanl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_atanf80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq atanl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.atan.f80(x86_fp80 %a)
   ret x86_fp80 %x
 }
 
-define fp128 @use_atanfp128(fp128 %a) nounwind {
-; CHECK-LABEL: use_atanfp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp  atanf128@PLT # TAILCALL
-  %x = call fp128 @llvm.atan.f128(fp128 %a)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_atanppc_fp128(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: use_atanppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq atanl@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.atan.ppcf128(ppc_fp128 %a)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.atan.f16(half)
 declare float @llvm.atan.f32(float)
 declare double @llvm.atan.f64(double)
 declare x86_fp80 @llvm.atan.f80(x86_fp80)
-declare fp128 @llvm.atan.f128(fp128)
-declare ppc_fp128 @llvm.atan.ppcf128(ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.atan2.ll b/llvm/test/CodeGen/X86/llvm.atan2.ll
index ef2e4be..b72cb10 100644
--- a/llvm/test/CodeGen/X86/llvm.atan2.ll
+++ b/llvm/test/CodeGen/X86/llvm.atan2.ll
@@ -1,80 +1,78 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_atan2f16(half %a, half %b) nounwind {
-; CHECK-LABEL: use_atan2f16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; CHECK-NEXT:    movaps %xmm1, %xmm0
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    movss %xmm0, (%rsp) # 4-byte Spill
-; CHECK-NEXT:    movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
-; CHECK-NEXT:    # xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    movss (%rsp), %xmm1 # 4-byte Reload
-; CHECK-NEXT:    # xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    callq atan2f@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.atan2.f16(half %a, half %b)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_atan2f32(float %a, float %b) nounwind {
-; CHECK-LABEL: use_atan2f32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp atan2f@PLT # TAILCALL
+; X86-LABEL: use_atan2f32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll atan2f
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_atan2f32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp atan2f@PLT # TAILCALL
   %x = call float @llvm.atan2.f32(float %a, float %b)
   ret float %x
 }
 
 define double @use_atan2f64(double %a, double %b) nounwind {
-; CHECK-LABEL: use_atan2f64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp atan2@PLT # TAILCALL
+; X86-LABEL: use_atan2f64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $28, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll atan2
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_atan2f64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp atan2@PLT # TAILCALL
   %x = call double @llvm.atan2.f64(double %a, double %b)
   ret double %x
 }
 
 define x86_fp80 @use_atan2f80(x86_fp80 %a, x86_fp80 %b) nounwind {
-; CHECK-LABEL: use_atan2f80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $40, %rsp
-; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    fstpt {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq atan2l@PLT
-; CHECK-NEXT:    addq $40, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_atan2f80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $28, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll atan2l
+; X86-NEXT:    addl $28, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_atan2f80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $40, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq atan2l@PLT
+; X64-NEXT:    addq $40, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.atan2.f80(x86_fp80 %a, x86_fp80 %b)
   ret x86_fp80 %x
 }
 
-define fp128 @use_atan2fp128(fp128 %a, fp128 %b) nounwind {
-; CHECK-LABEL: use_atan2fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp atan2f128@PLT # TAILCALL
-  %x = call fp128 @llvm.atan2.f128(fp128 %a, fp128 %b)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_atan2ppc_fp128(ppc_fp128 %a, ppc_fp128 %b) nounwind {
-; CHECK-LABEL: use_atan2ppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq atan2l@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.atan2.ppcf128(ppc_fp128 %a, ppc_fp128 %b)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.atan2.f16(half, half)
 declare float @llvm.atan2.f32(float, float)
 declare double @llvm.atan2.f64(double, double)
 declare x86_fp80 @llvm.atan2.f80(x86_fp80, x86_fp80)
-declare fp128 @llvm.atan2.f128(fp128, fp128)
-declare ppc_fp128 @llvm.atan2.ppcf128(ppc_fp128, ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.cos.ll b/llvm/test/CodeGen/X86/llvm.cos.ll
new file mode 100644
index 0000000..35c22b8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/llvm.cos.ll
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=GISEL-X64
+
+define float @test_cos_f32(float %Val) nounwind {
+; X86-LABEL: test_cos_f32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll cosf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_cos_f32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp cosf@PLT # TAILCALL
+;
+; GISEL-X64-LABEL: test_cos_f32:
+; GISEL-X64:       # %bb.0:
+; GISEL-X64-NEXT:    jmp cosf@PLT # TAILCALL
+  %res = call float @llvm.cos.f32(float %Val)
+  ret float %res
+}
+
+define double @test_cos_f64(double %Val) nounwind {
+; X86-LABEL: test_cos_f64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll cos
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_cos_f64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp cos@PLT # TAILCALL
+;
+; GISEL-X64-LABEL: test_cos_f64:
+; GISEL-X64:       # %bb.0:
+; GISEL-X64-NEXT:    jmp cos@PLT # TAILCALL
+  %res = call double @llvm.cos.f64(double %Val)
+  ret double %res
+}
+
+define x86_fp80 @test_cos_f80(x86_fp80 %Val) nounwind {
+; X86-LABEL: test_cos_f80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll cosl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_cos_f80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq cosl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: test_cos_f80:
+; GISEL-X64:       # %bb.0:
+; GISEL-X64-NEXT:    subq $24, %rsp
+; GISEL-X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT:    fstpt (%rsp)
+; GISEL-X64-NEXT:    callq cosl@PLT
+; GISEL-X64-NEXT:    addq $24, %rsp
+; GISEL-X64-NEXT:    retq
+  %res = call x86_fp80 @llvm.cos.f80(x86_fp80 %Val)
+  ret x86_fp80 %res
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.cosh.ll b/llvm/test/CodeGen/X86/llvm.cosh.ll
index 5e7582c..5f0c2f1 100644
--- a/llvm/test/CodeGen/X86/llvm.cosh.ll
+++ b/llvm/test/CodeGen/X86/llvm.cosh.ll
@@ -1,70 +1,70 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_coshf16(half %a) nounwind {
-; CHECK-LABEL: use_coshf16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    callq coshf@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.cosh.f16(half %a)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_coshf32(float %a) nounwind {
-; CHECK-LABEL: use_coshf32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp coshf@PLT # TAILCALL
+; X86-LABEL: use_coshf32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll coshf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_coshf32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp coshf@PLT # TAILCALL
   %x = call float @llvm.cosh.f32(float %a)
   ret float %x
 }
 
 define double @use_coshf64(double %a) nounwind {
-; CHECK-LABEL: use_coshf64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp cosh@PLT # TAILCALL
+; X86-LABEL: use_coshf64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll cosh
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_coshf64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp cosh@PLT # TAILCALL
   %x = call double @llvm.cosh.f64(double %a)
   ret double %x
 }
 
 define x86_fp80 @use_coshf80(x86_fp80 %a) nounwind {
-; CHECK-LABEL: use_coshf80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:    fldt 32(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq coshl@PLT
-; CHECK-NEXT:    addq  $24, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_coshf80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll coshl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_coshf80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq coshl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.cosh.f80(x86_fp80 %a)
   ret x86_fp80 %x
 }
 
-define fp128 @use_coshfp128(fp128 %a) nounwind {
-; CHECK-LABEL: use_coshfp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp  coshf128@PLT # TAILCALL
-  %x = call fp128 @llvm.cosh.f128(fp128 %a)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_coshppc_fp128(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: use_coshppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq coshl@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.cosh.ppcf128(ppc_fp128 %a)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.cosh.f16(half)
 declare float @llvm.cosh.f32(float)
 declare double @llvm.cosh.f64(double)
 declare x86_fp80 @llvm.cosh.f80(x86_fp80)
-declare fp128 @llvm.cosh.f128(fp128)
-declare ppc_fp128 @llvm.cosh.ppcf128(ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.sin.ll b/llvm/test/CodeGen/X86/llvm.sin.ll
new file mode 100644
index 0000000..1d2dcef
--- /dev/null
+++ b/llvm/test/CodeGen/X86/llvm.sin.ll
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=GISEL-X64
+
+define float @test_sin_f32(float %Val) nounwind {
+; X86-LABEL: test_sin_f32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll sinf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_sin_f32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp sinf@PLT # TAILCALL
+;
+; GISEL-X64-LABEL: test_sin_f32:
+; GISEL-X64:       # %bb.0:
+; GISEL-X64-NEXT:    jmp sinf@PLT # TAILCALL
+  %res = call float @llvm.sin.f32(float %Val)
+  ret float %res
+}
+
+define double @test_sin_f64(double %Val) nounwind {
+; X86-LABEL: test_sin_f64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll sin
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_sin_f64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp sin@PLT # TAILCALL
+;
+; GISEL-X64-LABEL: test_sin_f64:
+; GISEL-X64:       # %bb.0:
+; GISEL-X64-NEXT:    jmp sin@PLT # TAILCALL
+  %res = call double @llvm.sin.f64(double %Val)
+  ret double %res
+}
+
+define x86_fp80 @test_sin_f80(x86_fp80 %Val) nounwind {
+; X86-LABEL: test_sin_f80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll sinl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: test_sin_f80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq sinl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: test_sin_f80:
+; GISEL-X64:       # %bb.0:
+; GISEL-X64-NEXT:    subq $24, %rsp
+; GISEL-X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT:    fstpt (%rsp)
+; GISEL-X64-NEXT:    callq sinl@PLT
+; GISEL-X64-NEXT:    addq $24, %rsp
+; GISEL-X64-NEXT:    retq
+  %res = call x86_fp80 @llvm.sin.f80(x86_fp80 %Val)
+  ret x86_fp80 %res
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.sinh.ll b/llvm/test/CodeGen/X86/llvm.sinh.ll
index ba22842..de8a710 100644
--- a/llvm/test/CodeGen/X86/llvm.sinh.ll
+++ b/llvm/test/CodeGen/X86/llvm.sinh.ll
@@ -1,70 +1,70 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_sinhf16(half %a) nounwind {
-; CHECK-LABEL: use_sinhf16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    callq sinhf@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.sinh.f16(half %a)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_sinhf32(float %a) nounwind {
-; CHECK-LABEL: use_sinhf32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp sinhf@PLT # TAILCALL
+; X86-LABEL: use_sinhf32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll sinhf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_sinhf32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp sinhf@PLT # TAILCALL
   %x = call float @llvm.sinh.f32(float %a)
   ret float %x
 }
 
 define double @use_sinhf64(double %a) nounwind {
-; CHECK-LABEL: use_sinhf64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp sinh@PLT # TAILCALL
+; X86-LABEL: use_sinhf64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll sinh
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_sinhf64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp sinh@PLT # TAILCALL
   %x = call double @llvm.sinh.f64(double %a)
   ret double %x
 }
 
 define x86_fp80 @use_sinhf80(x86_fp80 %a) nounwind {
-; CHECK-LABEL: use_sinhf80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:    fldt 32(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq sinhl@PLT
-; CHECK-NEXT:    addq  $24, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_sinhf80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll sinhl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_sinhf80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq sinhl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.sinh.f80(x86_fp80 %a)
   ret x86_fp80 %x
 }
 
-define fp128 @use_sinhfp128(fp128 %a) nounwind {
-; CHECK-LABEL: use_sinhfp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp  sinhf128@PLT # TAILCALL
-  %x = call fp128 @llvm.sinh.f128(fp128 %a)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_sinhppc_fp128(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: use_sinhppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq sinhl@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.sinh.ppcf128(ppc_fp128 %a)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.sinh.f16(half)
 declare float @llvm.sinh.f32(float)
 declare double @llvm.sinh.f64(double)
 declare x86_fp80 @llvm.sinh.f80(x86_fp80)
-declare fp128 @llvm.sinh.f128(fp128)
-declare ppc_fp128 @llvm.sinh.ppcf128(ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.tan.ll b/llvm/test/CodeGen/X86/llvm.tan.ll
index 24b3003..3205551 100644
--- a/llvm/test/CodeGen/X86/llvm.tan.ll
+++ b/llvm/test/CodeGen/X86/llvm.tan.ll
@@ -1,70 +1,70 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_tanf16(half %a) nounwind {
-; CHECK-LABEL: use_tanf16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    callq tanf@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.tan.f16(half %a)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_tanf32(float %a) nounwind {
-; CHECK-LABEL: use_tanf32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp tanf@PLT # TAILCALL
+; X86-LABEL: use_tanf32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll tanf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_tanf32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp tanf@PLT # TAILCALL
   %x = call float @llvm.tan.f32(float %a)
   ret float %x
 }
 
 define double @use_tanf64(double %a) nounwind {
-; CHECK-LABEL: use_tanf64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp tan@PLT # TAILCALL
+; X86-LABEL: use_tanf64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll tan
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_tanf64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp tan@PLT # TAILCALL
   %x = call double @llvm.tan.f64(double %a)
   ret double %x
 }
 
 define x86_fp80 @use_tanf80(x86_fp80 %a) nounwind {
-; CHECK-LABEL: use_tanf80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:    fldt 32(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq tanl@PLT
-; CHECK-NEXT:    addq  $24, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_tanf80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll tanl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_tanf80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq tanl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.tan.f80(x86_fp80 %a)
   ret x86_fp80 %x
 }
 
-define fp128 @use_tanfp128(fp128 %a) nounwind {
-; CHECK-LABEL: use_tanfp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp  tanf128@PLT # TAILCALL
-  %x = call fp128 @llvm.tan.f128(fp128 %a)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_tanppc_fp128(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: use_tanppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq tanl@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.tan.ppcf128(ppc_fp128 %a)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.tan.f16(half)
 declare float @llvm.tan.f32(float)
 declare double @llvm.tan.f64(double)
 declare x86_fp80 @llvm.tan.f80(x86_fp80)
-declare fp128 @llvm.tan.f128(fp128)
-declare ppc_fp128 @llvm.tan.ppcf128(ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/llvm.tanh.ll b/llvm/test/CodeGen/X86/llvm.tanh.ll
index 7119c40..6911a68 100644
--- a/llvm/test/CodeGen/X86/llvm.tanh.ll
+++ b/llvm/test/CodeGen/X86/llvm.tanh.ll
@@ -1,70 +1,70 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
-
-define half @use_tanhf16(half %a) nounwind {
-; CHECK-LABEL: use_tanhf16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq __extendhfsf2@PLT
-; CHECK-NEXT:    callq tanhf@PLT
-; CHECK-NEXT:    callq __truncsfhf2@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call half @llvm.tanh.f16(half %a)
-  ret half %x
-}
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=X64,SDAG-X64
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
 
 define float @use_tanhf32(float %a) nounwind {
-; CHECK-LABEL: use_tanhf32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp tanhf@PLT # TAILCALL
+; X86-LABEL: use_tanhf32:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    flds {{[0-9]+}}(%esp)
+; X86-NEXT:    fstps (%esp)
+; X86-NEXT:    calll tanhf
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_tanhf32:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp tanhf@PLT # TAILCALL
   %x = call float @llvm.tanh.f32(float %a)
   ret float %x
 }
 
 define double @use_tanhf64(double %a) nounwind {
-; CHECK-LABEL: use_tanhf64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp tanh@PLT # TAILCALL
+; X86-LABEL: use_tanhf64:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpl (%esp)
+; X86-NEXT:    calll tanh
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_tanhf64:
+; X64:       # %bb.0:
+; X64-NEXT:    jmp tanh@PLT # TAILCALL
   %x = call double @llvm.tanh.f64(double %a)
   ret double %x
 }
 
 define x86_fp80 @use_tanhf80(x86_fp80 %a) nounwind {
-; CHECK-LABEL: use_tanhf80:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:    fldt 32(%rsp)
-; CHECK-NEXT:    fstpt (%rsp)
-; CHECK-NEXT:    callq tanhl@PLT
-; CHECK-NEXT:    addq  $24, %rsp
-; CHECK-NEXT:    retq
+; X86-LABEL: use_tanhf80:
+; X86:       # %bb.0:
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
+; X86-NEXT:    fstpt (%esp)
+; X86-NEXT:    calll tanhl
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    retl
+;
+; X64-LABEL: use_tanhf80:
+; X64:       # %bb.0:
+; X64-NEXT:    subq $24, %rsp
+; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; X64-NEXT:    fstpt (%rsp)
+; X64-NEXT:    callq tanhl@PLT
+; X64-NEXT:    addq $24, %rsp
+; X64-NEXT:    retq
   %x = call x86_fp80 @llvm.tanh.f80(x86_fp80 %a)
   ret x86_fp80 %x
 }
 
-define fp128 @use_tanhfp128(fp128 %a) nounwind {
-; CHECK-LABEL: use_tanhfp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    jmp  tanhf128@PLT # TAILCALL
-  %x = call fp128 @llvm.tanh.f128(fp128 %a)
-  ret fp128 %x
-}
-
-define ppc_fp128 @use_tanhppc_fp128(ppc_fp128 %a) nounwind {
-; CHECK-LABEL: use_tanhppc_fp128:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    callq tanhl@PLT
-; CHECK-NEXT:    popq %rax
-; CHECK-NEXT:    retq
-  %x = call ppc_fp128 @llvm.tanh.ppcf128(ppc_fp128 %a)
-  ret ppc_fp128 %x
-}
-
-declare half @llvm.tanh.f16(half)
 declare float @llvm.tanh.f32(float)
 declare double @llvm.tanh.f64(double)
 declare x86_fp80 @llvm.tanh.f80(x86_fp80)
-declare fp128 @llvm.tanh.f128(fp128)
-declare ppc_fp128 @llvm.tanh.ppcf128(ppc_fp128)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-X64: {{.*}}
+; GISEL-X86: {{.*}}
+; SDAG-X64: {{.*}}
+; SDAG-X86: {{.*}}