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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-01-31 20:48:11 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-01-31 20:48:11 +0000 |
| commit | 9eb085e6cf2e52a05d13f5b7da365add59cdb9b2 (patch) | |
| tree | 180b22b15c5aabbc6c0a303f5406f69da4738b1c | |
| parent | b843f7517949b7f1b2f098fe2aff6e459a5f1af8 (diff) | |
| download | llvm-9eb085e6cf2e52a05d13f5b7da365add59cdb9b2.zip llvm-9eb085e6cf2e52a05d13f5b7da365add59cdb9b2.tar.gz llvm-9eb085e6cf2e52a05d13f5b7da365add59cdb9b2.tar.bz2 | |
[Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering
llvm-svn: 323912
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll | 20 |
2 files changed, 24 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index bcef8b7..9535d0f 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3261,6 +3261,10 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { if (Subtarget.useHVXOps()) return LowerHvxMulh(Op, DAG); break; + case ISD::ANY_EXTEND_VECTOR_INREG: + if (Subtarget.useHVXOps()) + return LowerHvxExtend(Op, DAG); + break; } return SDValue(); } diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll new file mode 100644 index 0000000..bc859ae --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; This code causes any_extend_vector_inreg to appear in the selection DAG. +; Make sure that it is handled instead of crashing. +; CHECK: vmem + +target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" +target triple = "hexagon" + +define hidden fastcc void @fred() #0 { +b0: + %v1 = load i16, i16* undef, align 2 + %v2 = insertelement <16 x i16> undef, i16 %v1, i32 15 + %v3 = zext <16 x i16> %v2 to <16 x i32> + %v4 = shl nuw <16 x i32> %v3, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> + store <16 x i32> %v4, <16 x i32>* undef, align 4 + unreachable +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } |