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authorJim Lin <tclin914@gmail.com>2020-05-12 18:49:17 +0800
committerJim Lin <tclin914@gmail.com>2020-05-12 18:49:17 +0800
commit9d6064ec49ec189d2ff032927e41bb90ac471ae1 (patch)
treebdba6f83d1a5d4fbc03322f89e62e36a086ea02d
parente114bdf072d98756de289bfc0f3aefc4e34304ee (diff)
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Revert "[RISCV] Make CanLowerReturn protected for downstream maintenance"
This reverts commit d775841d7d6ee3e8bbf3a420590be9bb19433eaa.
-rw-r--r--llvm/lib/Target/RISCV/RISCVISelLowering.h11
1 files changed, 4 insertions, 7 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 825f397..0927a3e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -161,13 +161,6 @@ public:
Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override;
-protected:
- // This method is protected for customizing and reusing by inherited class.
- bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
- bool IsVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs,
- LLVMContext &Context) const override;
-
private:
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -181,6 +174,10 @@ private:
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &DL, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const override;
+ bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+ bool IsVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext &Context) const override;
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,